Algorithmic studies on PCB routing

As IC technology advances, the package size keeps shrinking while the pin count of a package keeps increasing. A modern IC package can have a pin count of thousands. As a result, a complex printed circuit board (PCB) can host more than ten thousand signal nets. Such a huge pin count and net count make manual design of packages and PCBs an extremely time-consuming and error-prone task. On the other hand, increasing clock frequency imposes various physical constraints on PCB routing. These constraints make traditional IC and PCB routers not applicable to modern PCB routing. To the best of our knowledge, there is no mature commercial or academic automated router that handles these constraints well. Therefore, automated PCB routers that are tuned to handle such constraints become a necessity in modern design. In this dissertation, we propose novel algorithms for three major aspects of PCB routing: escape routing, area routing and layer assignment. Escape routing for packages and PCBs has been studied extensively in the past. Network flow is pervasively used to model this problem. However, previous studies are incomplete in two senses. First, none of the previous works correctly model the diagonal capacity, which is essential for 45 degree routing in most packages and PCBs. As a result, existing algorithms may either produce routing solutions that violate the diagonal capacity or fail to output a legal routing even though one exists. Second, few works discuss the escape routing problem of differential pairs. In high-performance PCBs, many critical nets use differential pairs to transmit signals. How to escape differential pairs from a pin array is an important issue that has received too little attention in the literature. In this dissertation, we propose a new network flow model that guarantees the correctness when diagonal capacity is taken into consideration. This model leads to the first optimal algorithm for escape routing. We also extend our model to handle missing pins. We then propose two algorithms for the differential pair escape routing problem. The first one computes the optimal routing for a single differential pair while the second one is able to simultaneously route multiple differential pairs considering both routability and wire length. We then propose a two-stage routing scheme based on the two algorithms. In our routing scheme, the second algorithm is used to generate initial routing and the first algorithm is used to perform rip-up and reroute. Length-constrained routing is another very important problem for PCB routing. Previous length-constrained routers all have assumptions on the routing topology. We propose a routing scheme that is free of any restriction on the routing topology. The novelty of our proposed routing scheme is that we view the length-constrained routing problem as an area assignment problem and use a placement structure to help transform the area assignment problem into a mathematical programming problem. Experimental results show that our routing scheme can handle practical designs that previous routers cannot handle. For designs that they could handle, our router runs much faster. Length-constrained routing requires the escaped nets to have matching ordering along the boundaries of the pin arrays. However, in some practical designs, the net ordering might be mismatched. To address this issue, we propose a preprocessing step to untangle such twisted nets. We also introduce a practical routing style, which we call single-detour routing, to simplify the untangling problem. We discover a necessary and sufficient condition for the existence of single-detour routing solutions and present a dynamic programming based algorithm that optimally solves the problem. By integrating our algorithm into the bus router in a length-constrained router, we show that many routing problems that cannot be solved previously can now be solved with insignificant increase in runtime. The nets on a PCB are usually grouped into buses. Because of the high pin density of the packages, the buses need to be assigned into multiple routing layers. We propose a layer assignment algorithm to assign a set of buses into multiple layers without causing any conflict. Our algorithm guarantees to produce a layer assignment with minimum number of layers. The key idea is to transform the layer assignment problem into a bipartite matching problem. This research result is an improvement over a previous work, which is optimal for only one layer

Optimisation of Mobile Communication Networks - OMCO NET

The mini conference “Optimisation of Mobile Communication Networks” focuses on advanced methods for search and optimisation applied to wireless communication networks. It is sponsored by Research & Enterprise Fund Southampton Solent University. The conference strives to widen knowledge on advanced search methods capable of optimisation of wireless communications networks. The aim is to provide a forum for exchange of recent knowledge, new ideas and trends in this progressive and challenging area. The conference will popularise new successful approaches on resolving hard tasks such as minimisation of transmit power, cooperative and optimal routing

Rare events statistics of random walks on networks: localization and other dynamical phase transitions

Rare event statistics for random walks on complex networks are investigated using the large deviations formalism. Within this formalism, rare events are realized as typical events in a suitably deformed path-ensemble, and their statistics can be studied in terms of spectral properties of a deformed Markov transition matrix. We observe two different types of phase transition in such systems: (i) rare events which are singled out for sufficiently large values of the deformation parameter may correspond to {\em localized\/} modes of the deformed transition matrix, (ii) "mode-switching transitions" may occur as the deformation parameter is varied. Details depend on the nature of the observable for which the rare event statistics is studied, as well as on the underlying graph ensemble. In the present letter we report on the statistics of the average degree of the nodes visited along a random walk trajectory in Erd\H{o}s-R\'enyi networks. Large deviations rate functions and localization properties are studied numerically. For observables of the type considered here, we also derive an analytical approximation for the Legendre transform of the large-deviations rate function, which is valid in the large connectivity limit. It is found to agree well with simulations.Comment: 5 pages, 3 figure

Optimal Network Control in Partially-Controllable Networks

The effectiveness of many optimal network control algorithms (e.g., BackPressure) relies on the premise that all of the nodes are fully controllable. However, these algorithms may yield poor performance in a partially-controllable network where a subset of nodes are uncontrollable and use some unknown policy. Such a partially-controllable model is of increasing importance in real-world networked systems such as overlay-underlay networks. In this paper, we design optimal network control algorithms that can stabilize a partially-controllable network. We first study the scenario where uncontrollable nodes use a queue-agnostic policy, and propose a low-complexity throughput-optimal algorithm, called Tracking-MaxWeight (TMW), which enhances the original MaxWeight algorithm with an explicit learning of the policy used by uncontrollable nodes. Next, we investigate the scenario where uncontrollable nodes use a queue-dependent policy and the problem is formulated as an MDP with unknown queueing dynamics. We propose a new reinforcement learning algorithm, called Truncated Upper Confidence Reinforcement Learning (TUCRL), and prove that TUCRL achieves tunable three-way tradeoffs between throughput, delay and convergence rate

A framework for fine-grain synthesis optimization of operational amplifiers

This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability

Channel routing: Efficient solutions using neural networks

Neural network architectures are effectively applied to solve the channel routing problem. Algorithms for both two-layer and multilayer channel-width minimization, and constrained via minimization are proposed and implemented. Experimental results show that the proposed channel-width minimization algorithms are much superior in all respects compared to existing algorithms. The optimal two-layer solutions to most of the benchmark problems, not previously obtained, are obtained for the first time, including an optimal solution to the famous Deutch\u27s difficult problem. The optimal solution in four-layers for one of the be lchmark problems, not previously obtained, is obtained for the first time. Both convergence rate and the speed with which the simulations are executed are outstanding. A neural network solution to the constrained via minimization problem is also presented. In addition, a fast and simple linear-time algorithm is presented, possibly for the first time, for coloring of vertices of an interval graph, provided the line intervals are given