Illegal Marijuana Cultivation on Public Lands: Our Federalism on a Very Bad Trip

Fueled by increasing demand for marijuana, illegal cultivation of the drug on public lands is causing massive environmental harm. The federal government lacks the resources to wage what would be a difficult and costly campaign to eradicate these illegal grow sites and instead focuses its limited resources on enforcing the federal marijuana ban. Marijuana decriminalization might allow legally grown marijuana to squeeze out its illegal counterpart, but the political likelihood of decriminalization is low. The key is reducing demand for the illegal drug by changing public buying preferences. However, doing this depends on an available legal alternative. This Article discusses several behavioral modification approaches as a way of changing consumer preferences and possible ways to resolve the current conflict between state marijuana legalization and its federal criminalization

Helping or Hindering Life? The Ramifications of Overturning \u3cem\u3eRoe v. Wade \u3c/em\u3eas It Relates to the Criminal Justice System

Part I of this Comment explores 2001 research by John Donohue and Steven Levitt finding that legalized abortion significantly contributed to a decrease in crime starting in 1991. Part II of this Comment will explore the background of abortion. Part III will highlight the scope of abortion following Roe by analyzing Donohue and Levitt’s abortion-crime link. Part IV of this Comment will succinctly summarize these conclusions

The Question of Descriptors for Academic Writing in European Language Framework: a Critical View

Since the 1960s, with the influx of a great number of students, both native and non-native, with little experience in formal academic discourse, universities in the English-speaking world have become increasingly aware of the need to offer specific instruction in writing skills. This situation required a clearer definition of what the characteristics of this particular type of writing might be (Grabe & Kaplan 1996) and it became apparent that many of the existing teaching materials concentrated overly on normative, grammatical considerations and not on a broader perspective based on discursive competence. Therefore, since the 1990s, there has been more emphasis on the analysis of the rhetorical conventions of various genres, including cross-linguistic comparisons (Connor 1995; Flowerdew 2000; Hyland 2002; Neff et al. 2004; Neff and Dafouz 2008).Because of the utilization of English as a “lingua franca” in the global community (Gnutzman and Intemann 2005) and the growth of student exchange programs within Europe, it has become progressively evident that both students and teachers require a clear set of guidelines, such as those provided by the EU framework descriptors for various areas of linguistic competency. But, as the difficulties experienced by non-native writers of academic English are very genre specific and appear to be largely independent of purely linguistic competency (many native novice writers also find academic writing problematic), the EU descriptors for academic work are too broad for the type of writing that our students must carry out in tertiary institutions.While much work is clearly being done within universities and colleges to address the prototypical academic writing skills in English, it would be helpful for all concerned if more specific guidelines could be shared. Thus, one major aim of this study is to draw up a series of structural and rhetorical descriptors and evaluate our students’ written production before and after using them in order to test their relevance for our syllabus and perhaps for use by a wider audience in the future

Placement-Driven Technology Mapping for LUT-Based FPGAs

In this paper, we study the problem of placement-driven technology mapping for table-lookup based FPGA architectures to optimize circuit performance. Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay. Later works such as Flowmap-d[7], Bias-Clus[4] and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3 % on the average

Timing-Driven Macro Placement

Placement is an important step in the process of finding physical layouts for electronic computer chips. The basic task during placement is to arrange the building blocks of the chip, the circuits, disjointly within a given chip area. Furthermore, such positions should result in short circuit interconnections which can be routed easily and which ensure all signals arrive in time. This dissertation mostly focuses on macros, the largest circuits on a chip. In order to optimize timing characteristics during macro placement, we propose a new optimistic timing model based on geometric distance constraints. This model can be computed and evaluated efficiently in order to predict timing traits accurately in practice. Packing rectangles disjointly remains strongly NP-hard under slack maximization in our timing model. Despite of this we develop an exact, linear time algorithm for special cases. The proposed timing model is incorporated into BonnMacro, the macro placement component of the BonnTools physical design optimization suite developed at the Research Institute for Discrete Mathematics. Using efficient formulations as mixed-integer programs we can legalize macros locally while optimizing timing. This results in the first timing-aware macro placement tool. In addition, we provide multiple enhancements for the partitioning-based standard circuit placement algorithm BonnPlace. We find a model of partitioning as minimum-cost flow problem that is provably as small as possible using which we can avoid running time intensive instances. Moreover we propose the new global placement flow Self-Stabilizing BonnPlace. This approach combines BonnPlace with a force-directed placement framework. It provides the flexibility to optimize the two involved objectives, routability and timing, directly during placement. The performance of our placement tools is confirmed on a large variety of academic benchmarks as well as real-world designs provided by our industrial partner IBM. We reduce running time of partitioning significantly and demonstrate that Self-Stabilizing BonnPlace finds easily routable placements for challenging designs – even when simultaneously optimizing timing objectives. BonnMacro and Self-Stabilizing BonnPlace can be combined to the first timing-driven mixed-size placement flow. This combination often finds placements with competitive timing traits and even outperforms solutions that have been determined manually by experienced designers

On the Use of Directed Moves for Placement in VLSI CAD

Search-based placement methods have long been used for placing integrated circuits targeting the field programmable gate array (FPGA) and standard cell design styles. Such methods offer the potential for high-quality solutions but often come at the cost of long run-times compared to alternative methods. This dissertation examines strategies for enhancing local search heuristics---and in particular, simulated annealing---through the application of directed moves. These moves help to guide a search-based optimizer by focusing efforts on states which are most likely to yield productive improvement, effectively pruning the size of the search space. The engineering theory and implementation details of directed moves are discussed in the context of both field programmable gate array and standard cell designs. This work explores the ways in which such moves can be used to improve the quality of FPGA placements, improve the robustness of floorplan repair and legalization methods for mixed-size standard cell designs, and enhance the quality of detailed placement for standard cell circuits. The analysis presented herein confirms the validity and efficacy of directed moves, and supports the use of such heuristics within various optimization frameworks

Spartan Daily, November 2, 1979

Volume 73, Issue 43https://scholarworks.sjsu.edu/spartandaily/6541/thumbnail.jp