Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits

 Leakage power is the dominant source of power dissipation innanometer technology. As per the International Technology Roadmap forSemiconductors (ITRS) static power dominates dynamic power with theadvancement in technology. One of the well-known techniques used forleakage reduction is Input Vector Control (IVC). Due to stacking effect inIVC, it gives less leakage for the Minimum Leakage Vector (MLV) appliedat inputs of test circuit. This paper introduces Particle Swarm Optimization(PSO) algorithm to the field of VLSI to find minimum leakage vector.Another optimization algorithm called Genetic algorithm (GA) is alsoimplemented to search MLV and compared with PSO in terms of number ofiterations. The proposed approach is validated by simulating few testcircuits. Both GA and PSO algorithms are implemented in Verilog HDLand the simulations are carried out using Xilinx 9.2i. From the simulationresults it is found that PSO based approach is best in finding MLVcompared to Genetic based implementation as PSO technique uses lessruntime compared to GA. To the best of the author’s knowledge PSOalgorithm is used in IVC technique to optimize power for the first time andit is quite successful in searching MLV

On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test and Its Application to A Digital Sensor

An aging-tolerant ring oscillator (RO) has been proposed for a digital temperature and voltage sensor. This paper discusses on the effectiveness of aging-tolerance of the ROs through accelerated life test for a test chip with 65nm CMOS technology. The progress of delay degradation of the ROs is examined, and influence of delay degradation on measurement accuracy of the sensor is investigated. Experimental results show that the aging-tolerant ROs can mitigate delay degradation, and that the measurement errors of the sensor can be reduced. Compared with a sensor consisting of an aging-intolerant RO, temperature and voltage errors are reduced 2.5°C and 32mV, respectively.29th IEEE Asian Test Symposium (ATS\u2720), November 22-25, 2020, Penang, Malaysia（オンライン開催に変更

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

Resilient Design for Process and Runtime Variations

The main objective of this thesis is to tackle the impact of parameter variations in order to improve the chip performance and extend its lifetime