Unleashing the power of decentralized serverless IoT dataflow architecture for the Cloud-to-Edge Continuum: a performance comparison

The advent of new computing and communication trends that link pervasive data sources and consumers, such as Edge Computing, 5G and IIoT, has led to the development of the Cloud-to-Edge Continuum in order to take advantage of the resources available in massive IoT scenarios and to conduct data analysis to leverage intelligence at all levels. This paper outlines the challenging requirements of this novel IoT context and presents an innovative IoT framework to develop dataflow applications for data-centric environments. The proposed design takes advantage of decentralized Pub/Sub communication and serverless nanoservice architecture, using novel technologies such as Zenoh and WebAssembly, respectively, to implement lightweight services along the Cloud-to-Edge infrastructure. We also describe some use cases to illustrate the benefits and concerns of the coming IoT generation, giving a communication performance comparison of Zenoh over brokered MQTT strategies.Ministerio de Universidades | Ref. FPU19/01284Agencia Estatal de Investigación | Ref. PCI2020-112174Agencia Estatal de Investigación | Ref. PID2020-113795RB-C33Agencia Estatal de Investigación | Ref. PID2020-116329GB-C21Xunta de Galicia | Ref. GRC-ED431C2022/04 T254Universidade de Vigo/CISU

Holistic Performance Analysis and Optimization of Unified Virtual Memory

The programming difficulty of creating GPU-accelerated high performance computing (HPC) codes has been greatly reduced by the advent of Unified Memory technologies that abstract the management of physical memory away from the developer. However, these systems incur substantial overhead that paradoxically grows for codes where these technologies are most useful. While these technologies are increasingly adopted for use in modern HPC frameworks and applications, the performance cost reduces the efficiency of these systems and turns away some developers from adoption entirely. These systems are naturally difficult to optimize due to the large number of interconnected hardware and software components that must be untangled to perform thorough analysis. In this thesis, we take the first deep dive into a functional implementation of a Unified Memory system, NVIDIA UVM, to evaluate the performance and characteristics of these systems. We show specific hardware and software interactions that cause serialization between host and devices. We further provide a quantitative evaluation of fault handling for various applications under different scenarios, including prefetching and oversubscription. Through lower-level analysis, we find that the driver workload is dependent on the interactions among application access patterns, GPU hardware constraints, and Host OS components. These findings indicate that the cost of host OS components is significant and present across UM implementations. We also provide a proof-of-concept asynchronous approach to memory management in UVM that allows for reduced system overhead and improved application performance. This study provides constructive insight into future implementations and systems, such as Heterogeneous Memory Management