Performance Analysis of Karatsuba Multiplication Algorithm for Different Bit Lengths

AbstractIn computer arithmetic, multiplication is one of the most significant operations. Multiplication is used in many operations such as division, squaring and computing reciprocal. In addition, the efficiency of multiplication is crucial due to the use of digital signal processing applications such as correlation, filtering, frequency analysis and image processing. Karatsuba algorithm is one of the algorithms developed for increasing the efficiency and reducing the cost in order to simplify multiplication. In this study, the performance of Karatsuba algorithm is analyzed in terms of the number of multiplication and the total process time for different bit lengths

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques. Further, the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator

ZOT-MK: a new algorithm for big integer multiplication[QA75].

Pendaraban nombor besar banyak digunakan dalam pengkomputeran saintifik. Walau bagaimanapun, terdapat hanya beberapa alogritma yang ada kini, memperoleh keefisienan mereka melalui pendaraban integer besar. Multiplication of big numbers is being used heavily in scientific computation. However, there are only a few existing algorithms today that gain their efficiency through the multiplication of the big integer characteristic

Hardware Implementation of Bit-Parallel Finite Field Multipliers Based on Overlap-free Algorithm on FPGA

Cryptography can be divided into two fundamentally different classes: symmetric-key and public-key. Compared with symmetric-key cryptography, where the complexity of the security system relies on a single key between receiver and sender, public-key cryptographic system using two separate but mathematically related keys. Finite field multiplication is a key operation used in all cryptographic systems relied on finite field arithmetic as it not only is computationally complex but also one of the most frequently used finite field operations. Karatsuba algorithm and its generalization are most often used to construct multiplication architectures with significantly improved in these decades. However, one of its optimized architecture called Overlap-free Karatsuba algorithm has been mentioned by fewer people and even its implementation on FPGA has not been mentioned by anyone. After completion of a detailed study of this specific algorithm, this thesis has proposed implementation of modified Overlap-free Karatsuba algorithm on Xilinx Spartan-605. Applied this algorithm and its specific architecture, reduced gates or shorten critical path will be achieved for the given value of n.Optimized multiplication architecture, generated from proposed modified Overlap-free Karatsuba algorithm and applied on FPGA board,over NIST recommended fields (n = 128), are presented and analysed in detail. Compared with existing works with sub-quadratic space and time complexities, the proposed modified algorithm is highly recommended module and have improved on both space and time complexities. At last, generalization of proposed modified algorithm is suitable for much larger size of finite fields, and improvements of FPGA itself have been discussed

An Efficient Elliptic Curve Cryptography Arithmetic Using Nikhilam Multiplication

Multiplication is one of the most important operation in Elliptic Curve Cryptography (ECC) arithmetic. For point addition and point doubling in ECC scalar (integer) multiplication is required. In higher order classical (standard) multiplication many intermediate operations are required. Reduced operation in multiplication will increase the functional speed of ECC arithmetic. These goals can be achieved using ancient multiplication algorithm namely Nikhilam Sutra. Nikhilam Sutra is one of the Sutra (algorithm) within 16 Vedic mathematics Sutras (algorithms). Nikhilam Sutra is efficient for multiplying two large decimal numbers. The Sutra reduces multiplication of two large numbers into two smaller numbers multiplication. The functional speed of Elliptic Curve Cryptography can be increased using Nikhilam method for scalar multiplication