Design of hardware-orientated security towards trusted electronics.

While the Internet of Things (IoT) becomes one of the critical components in the cyber-physical system of industry 4.0, its root of trust still lacks consideration. The purpose of this thesis was to increase the root of trust in electronic devices by enhance the reliability, testability, and security of the bottom layer of the IoT system, which is the Very Large-Scale Integration (VLSI) device. This was achieved by implement a new class of security primitive to secure the IJTAG network as an access point for testing and programming. The proposed security primitive expands the properties of a Physically Unclonable Function (PUF) to generate two different responses from a single challenge. The development of such feature was done using the ring counter circuit as the source of randomness of the PUF to increase the efficiency of the proposed PUF. The efficiency of the newly developed PUF was measured by comparing its properties with the properties of a legacy PUF. The randomness test done for the PUF shows that it has a limitation when implemented in sub-nm devices. However, when it was implemented in current 28nm silicon technology, it increases the sensitivity of the PUF as a sensor to detect malicious modification to the FPGA configuration file. Moreover, the efficiency of the developed bimodal PUF increases by 20.4% compared to the legacy PUF. This shows that the proposed security primitive proves to be more dependable and trustworthy than the previously proposed approach.Samie, Mohammad (Associate)PhD in Transport System

Reliability and security in wellbeing monitoring embedded systems

Dissertação para obtenção do Grau de Mestre em Engenharia Informática e de ComputadoresAo longo dos últimos anos, a fiabilidade e a segurança dos sistemas embebidos utilizados em áreas críticas, como a saúde e o sector automóvel, têm suscitado um interesse crescente na comunidade científica e ganho maior consciencialização entre o público em geral. Esta tese aborda a modelação e a implementação de uma arquitetura software fiável e segura para um sistema embebido focado na aquisição e processamento de sinais fisiológicos, em particular o eletrocardiograma (ECG). O trabalho realizado visou o CardioWheel, um projeto em curso desenvolvido pela CardioID Technologies, destinado a aplicações nas áreas da saúde e do automóvel. As particularidades destas áreas quanto aos seus requisitos de segurança e proteção dos utilizadores servem de caso de estudo para mostrar as vantagens da arquitetura desenvolvida. Assim, no estudo realizado foi feito o levantamento dos requisitos do sistema que foram utilizados para projetar a máquina de estados da arquitetura em UML, a qual foi validada formalmente utilizando a ferramenta Uppaal e o modelo de autómatos finitos temporizados. Também foi feita uma análise de ameaças à arquitetura para validar os aspetos relacionados com a segurança. A arquitetura foi desenvolvida para microcontroladores ESP32 usando o ecossistema ESP-IDF e o FreeRTOS, para o que foram consideradas camadas independentes de hardware. A camada de comunicação é baseada no protocolo Bluetooth Low Energy (BLE) e permite a transmissão dos dados do nó final para um gateway e, posteriormente, para um servidor na nuvem. A operação de atualização de firmware usando o componente Over-The-Air (OTA) foi também implementada e validada quanto à sua segurança. A arquitetura foi, inicialmente, avaliada e validada usando um protótipo laboratorial. Posteriormente, foi utilizada para realizar uma pequena série de produção do CardioWheel em que se utilizaram as estratégias de validação propostas no contexto do projeto ESCEL KDT Valu3s. Também foi realizado um ensaio pré-médico no Hospital de Santa Marta usando o CardioWheel com a arquitetura proposta, que permitiu validar a sua fiabilidade e capacidades quando comparado com um eletrocardiógrafo clínico.Recently, the reliability and cybersecurity aspects of embedded systems for critical domains, such as health and automotive, has increased interest in the research community and awareness to the general public. This thesis addresses the modelling and the implementation of a reliable and secure software architecture for an embedded system aimed at the acquisition and processing of physiological signals, in particular the electrocardiogram (ECG). The work focused CardioWheel, an ongoing project developed by CardioID Technologies, targeting health and automotive applications. These domains demand special requirements for safety and security, and serve as a showcase for the proposed architecture. Accordingly, suitable requirements were first established and the architecture state machine was developed using UML and formally validated using Uppaal and Timed Automata modelling. Then, the threat analysis of the architecture was conducted. Finally, the implementation was realized for an ESP32 microcontroller using the FreeRTOS, the ESP-IDF ecosystem, and specially developed hardware independent layers. The communication layer is based on Bluetooth Low Energy (BLE) and allows the transmission of the data from the end-node to a gateway and finally to the cloud. The system has a Over-The-Air (OTA) component that enables the update of the firmware and the security of this operation was also validated. The proposed architecture was firstly validated using a laboratory prototype. Then, it was deployed to build a small production series of CardioWheel incorporating validation strategies proposed within the context of the ESCEL KDT Valu3s project. Also, a pre-medical trial was conducted at the Hospital de Santa Marta, confirming the reliability and capabilities of our system against a clinical ground-truth.N/

JTAG Fault Injection Attack

International audienceFault injection attacks are widespread in thedomain of smart cards and microcontrollers but have not been yet democratized on complex embedded microprocessors such as systems-on-chip (SoC) that can be found in smart phones, tablets and automotive systems. The main explanation is the difficulty involved in injecting a fault at the right place and at the right time to make these attacks effective on such devices. However for development and debugging, these devices provide new tools that could be considered as possibly enabling attacks. One such tool, the JTAG debug tool is present on most electronic devices today. In this paper, we present the first fault injection attack based on JTAG. Using the example of a privilege escalation attack, we detail how this tool can be used either to check the feasibility of this attack by fault injection or to perform an actual attack