Channel routing optimization using a genetic algorithm

A modified approach for the application of Genetic Algorithm (GA) to the Channel Routing Problem has been proposed. The code based on the algorithm proposed in [1] has been implemented for the GA procedures of Initial Population Generation, Crossover, Mutation and Selection. A few improvements over the existing work have been made and the results so far obtained have been encouraging. Further experimentation is being done on the algorithm and other ideas generated during the development of the code are being implemented for faster convergence of the algorithm and for generation of more efficient results. Also application of variations of the GA technique like Vector GA and even other computationally intelligent techniques like Particle Swarm Optimization to the channel routing problem is being thought of

Some NP-Complete Problems in the Physical Design of Digital Integrated Circuits

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / SRC-87-DP-109HA

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Secure Physical Design

An integrated circuit is subject to a number of attacks including information leakage, side-channel attacks, fault-injection, malicious change, reverse engineering, and piracy. Majority of these attacks take advantage of physical placement and routing of cells and interconnects. Several measures have already been proposed to deal with security issues of the high level functional design and logic synthesis. However, to ensure end-to-end trustworthy IC design flow, it is necessary to have security sign-off during physical design flow. This paper presents a secure physical design roadmap to enable end-to-end trustworthy IC design flow. The paper also discusses utilization of AI/ML to establish security at the layout level. Major research challenges in obtaining a secure physical design are also discussed

Queensland Institute of Technology: Handbook 1988

The Queensland Institute of Technology handbook gives an outline of the faculties and subject offerings available that were offered by QIT