Hardware modeling of binary coded decimal adder in FPGA

There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (R-C) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device

Biblioteca Genérica de Pré-Processamento de Imagem em FPGA aplicada a Sistemas de Visão Industrial

A evolução tecnológica e a necessidade da sociedade atual possuir produtos de maior qualidade, provocou um aumento de complexidade nos sistemas de visão industrial im- plicando a integração de mais hardware na sua constituição com a finalidade de melhorar a sua eficiência. Na presente dissertação, o objetivo consiste na implementação de uma biblioteca genérica de métodos para execução em FPGA, em tempo real, com a finalidade de diminuir o tempo de processamento de imagem em sistemas de visão. O seu desen- volvimento teve como base a especificação de filtros em VHDL e a sua implementação na plataforma Zybo Z7-20. As frames processadas são transmitidas para CPU via Ethernet (UDP), possibilitando a integração do projeto em aplicações reais e a validação dos méto- dos. Foi realizada uma comparação entre o tempo de processamento de todos algoritmos desenvolvidos em duas plataformas (CPU e FPGA), assim como, a integração num sis- tema de visão industrial. Os resultados obtidos demonstraram ser positivos, visto que, a execução do pré-processamento em FPGA em tempo real acrescenta um atraso à imagem original na ordem dos nanossegundos, enquanto que, em CPU existe um acréscimo de tempo na ordem dos milissegundos para processar uma frame. Por fim, foi também rea- lizada a comparação de tempos com uma solução baseada em GPU, na qual, se verificou que quando executado o pré-processamento em FPGA são obtidos melhores resultados.The technological evolution and society need to own the best quality products induced an increase in industrial vision systems complexity requiring more hardware to improve its efficiency. The objective of this work is the development of a generic pre-processing FPGA library, to accelerate real time industrial vision systems. Its development was based on the design of VHDL filters, implemented on a Zybo Z7-20 platform. The processed frames are transmitted to a CPU by Ethernet protocol (UDP) to enable the project integration in real applications and the methods validation. The execution time of all filters was compared in two platforms (FPGA and CPU) followed by the project integration in an industrial vision system. The obtained results were positive, where the FPGA solution in real-time only adds a nanoseconds range delay to the execution time of the original image, while the CPU solution adds a milliseconds range delay to process a frame. Lastly, a comparison of execution times with a GPU-based solution was also performed, in which it was conluded that the FPGA pre-processing algorithms achieve better results

Robustness and durability aspects in the design of power management circuits for IoT applications

With the increasing interest in the heterogeneous world of the “Internet of Things” (IoT), new compelling challenges arise in the field of electronic design, especially concerning the development of innovative power management solutions. Being this diffusion a consolidated reality nowadays, emerging needs like lifetime, durability and robustness are becoming the new watchwords for power management, being a common ground which can dramatically improve service life and confidence in these devices. The possibility to design nodes which do not need external power supply is a crucial point in this scenario. Moreover, the development of autonomous nodes which are substantially maintenance free, and which therefore can be placed in unreachable or harsh environments is another enabling aspect for the exploitation of this technology. In this respect, the study of energy harvesting techniques is increasingly earning interest again. Along with efficiency aspects, degradation aspects are the other main research field with respect to lifetime, durability and robustness of IoT devices, especially related to aging mechanisms which are peculiar in power management and power conversion circuits, like for example battery wear during usage or hot-carrier degradation (HCD) in power MOSFETs. In this thesis different aspects related to lifetime, durability and robustness in the field of power management circuits are studied, leading to interesting contributions. Innovative designs of DC/DC power converters are studied and developed, especially related to reliability aspects of the use of electrochemical cells as power sources. Moreover, an advanced IoT node is proposed, based on energy harvesting techniques, which features an intelligent dynamically adaptive power management circuit. As a further contribution, a novel algorithm is proposed, which is able to effectively estimate the efficiency of a DC/DC converter for photovoltaic applications at runtime. Finally, an innovative DC/DC power converter with embedded monitoring of hot-carrier degradation in power MOSFETs is designed