150,895 research outputs found
A low-voltage CMOS multiplier for RF applications
This work is part of a project funded under the Fourth Italian-Maltese Financial Protocol.A low-voltage analog multiplier operating at 1.2 V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit was designed using standard 0.6 /spl mu/m CMOS technology. Simulation results indicate an IP3 of 4.9 dBm and a spur free dynamic range of 45 dB.peer-reviewe
Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity
The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-642-54420-0_45Unlike other previous techniques, the recently proposed Hard Error
Recovery (HER) fault-tolerant cache provides 100% fault-coverage in L1 data
caches. This full coverage makes the HER cache appropiate for fault-dominated
future technology nodes.
An n-way set-associative HER cache implements one cache way with fast
SRAM banks and the remaining ways with eDRAM banks to address power and
area. Since the number of eDRAM cache blocks used in a specific HER cache
organization depends on the cache associativity (i.e., the implemented number of
ways), we expect that the performance and energy consumption provided by a
given HER cache design strongly depends on the cache geometry.
In this work we study the behavior of the HER cache design when applied to
a highly associative L1 cache like those found in some modern microprocessors.
In particular this work explores a 32KB 8-way associative L1 data cache such as
the one used in Intel Haswell microarchitecture.
Experimental results show that, at low-power modes compared to a conventional
cache with the same storage capacity and number of ways, area, leakage
power, and dynamic energy savings of a 4-way HER cache are by 25%, 85%,
and 62%, respectively. These percentages are further improved (by 40%, 89%,
and 68%, respectively) when the cache associativity is increased to 8 ways, while
the performance loss with respect to both an 8-way conventional cache and the
4-way HER cache is minimal.This work was supponed by Generalitat de Catalunya (200950R1250), by FP7 program of the European Commission (TRAMS-248789), by Spanish Ministerio de EconomĂa y Competitividad (MINECO) and by FEDER funds
under Grant TlN2012-38341-C04-01 and TIN2010-18368.Lorente GarcĂ©s, VJ.; Valero BresĂł, A.; Canal, R. (2014). Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity. En Euro-Par 2013: Parallel Processing Workshops. Springer. 454-464. https://doi.org/10.1007/978-3-642-54420-0_45S454464Bhavnagarwala, A.J., et al.: The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability. IEEE Journal of Solid-State Circuits 36(4), 658â665 (2001)Mukhopadhyay, S., et al.: Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(12), 1859â1880 (2005)Shirvani, P.P., McCluskey, E.J.: PADded Cache: A New Fault-Tolerance Technique for Cache Memories. In: Proceedings of the 17th IEEE VLSI Test Symposium, pp. 440â445 (1999)Wilkerson, C., et al.: Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. In: Proceedings of the 35th Annual International Symposium on Computer Architecture, pp. 203â214 (2008)Agarwal, A., et al.: Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture. IEEE Journal of Solid-State Circuits 40(9), 1804â1814 (2005)Ansari, A., et al.: Archipelago: A Polymorphic Cache Design for Enabling Robust Near-Threshold Operation. In: Proceedings of the 17th International Symposium on High Performance Computer Architecture, pp. 539â550 (2011)Nomura, S., et al.: Sampling + DMR: Practical and Low-overhead Permanent Fault Detection. In: Proceedings of the 38th Annual International Symposium on Computer Architecture, pp. 201â212 (2011)Sinharoy, B., et al.: IBM POWER7 multicore server processor. IBM Journal of Research and Development 55(3) (2011)Lorente, V., et al.: Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. In: Proceedings of the Design, Automation, and Test in Europe Conference, pp. 83â88 (2013)Kanter, D.: Intelâs Haswell CPU Microarchitecture, âReal World Technologiesâ (November 13, 2012), http://www.realworldtech.com/haswell-cpu/Paul, S., et al.: Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Transactions on Computers 60(1), 20â34 (2011)Alameldeen, A.R., et al.: Adaptive Cache Design to Enable Reliable Low-Voltage Operation. IEEE Transactions on Computers 60, 50â63 (2011)Dreslinski, R.G., et al.: Reconfigurable Energy Efficient Near Threshold Cache Architectures. In: Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, pp. 459â470 (2008)Wilkerson, C., et al.: Reducing Cache Power with Low-Cost, Multi-bit Error-Correcting Codes. In: Proceedings of the 37th Annual International Symposium on Computer Architecture, pp. 83â93 (2010)Burger, D., Austin, T.M.: The SimpleScalar Tool Set, Version 2.0. ACM SIGARCH Computer Architecture News 25(3), 13â25 (1997)Thoziyoor, S., et al.: CACTI 5.1. Hewlett-Packard Laboratories, Palo Alto, Technical Report (2008)spec2000: Standard Performance Evaluation Corporation, http://www.spec.org/cpu2000Kulkarni, J.P., et al.: A 160 mV, Fully Differential, Robust Schmitt Trigger Based Sub-threshold SRAM. In: Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 171â176 (2007)Keeth, B., et al.: DRAM Circuit Design. Fundamental and High-Speed Topics. John Wiley and Sons, Inc., Hoboken (2008)Mueller, W., et al.: Challenges for the DRAM Cell Scaling to 40nm. In: IEEE International Electron Devices Meeting 4, pp. 336â339 (2005
Efficient and Secure Group Key Management in IoT using Multistage Interconnected PUF
Secure group-oriented communication is crucial to a wide range of
applications in Internet of Things (IoT). Security problems related to
group-oriented communications in IoT-based applications placed in a
privacy-sensitive environment have become a major concern along with the
development of the technology. Unfortunately, many IoT devices are designed to
be portable and light-weight; thus, their functionalities, including security
modules, are heavily constrained by the limited energy resources (e.g., battery
capacity). To address these problems, we propose a group key management scheme
based on a novel physically unclonable function (PUF) design: multistage
interconnected PUF (MIPUF) to secure group communications in an
energy-constrained environment. Our design is capable of performing key
management tasks such as key distribution, key storage and rekeying securely
and efficiently. We show that our design is secure against multiple attack
methods and our experimental results show that our design saves 47.33% of
energy globally comparing to state-of-the-art Elliptic-curve cryptography
(ECC)-based key management scheme on average.Comment: 6 pages, 4 figures, International Symposium on Low Power Electronics
and Desig
PS-Cache: an energy-efficient cache design for chip multiprocessors
The final publication is available at Springer via http://dx.doi.org/10.1007/s11227-014-1288-5Power consumption has become a major design concern in current high-performance chip multiprocessors, and this problem exacerbates with the number of core counts. A significant fraction of the total power budget is often consumed by on-chip caches, thus important research has focused on reducing energy consumption in these structures. To enhance performance, on-chip caches are being deployed with a high associativity degree. Consequently, accessing concurrently all the ways in the cache set is costly in terms of energy. This paper presents the PS-Cache architecture, an energy-efficient cache design that reduces the number of accessed ways without hurting the performance. The PS-Cache takes advantage of the private-shared knowledge of the referenced block to reduce energy by accessing only those ways holding the kind of block looked up. Experimental results show that, on average, the PS-Cache architecture can reduce the dynamic energy consumption of L1 and L2 caches by 22 and 40%, respectively.This work has been jointly supported by the MINECO and European Commission
(FEDER funds) under the project TIN2012-38341-C04-01 and the Fundaciâon Seneca-Agencia de Ciencia
y TecnologĂa de la RegiĂłn de Murcia under the project JĂłvenes LĂderes en InvestigaciĂłn 18956/JLI/13.Valls, JJ.; Ros Bardisa, A.; Sahuquillo BorrĂĄs, J.; GĂłmez Requena, ME. (2015). PS-Cache: an energy-efficient cache design for chip multiprocessors. Journal of Supercomputing. 71(1):67-86. https://doi.org/10.1007/s11227-014-1288-5S6786711Balasubramonian R, Jouppi NP, Muralimanohar N (2011) Multi-core cache hierarchies. In: Synthesis lectures on computer architecture. Morgan & Claypool Publishers, San RafaelHennessy JL, Patterson DA (2011) Computer architecture, fifth edition: a quantitative approach, 5th edn. Morgan Kaufmann Publishers Inc., San FranciscoSinharoy B, Kalla R, Starke WJ, Le HQ, Cargnoni R, Van Norstrand JA, Ronchetti BJ, Stuecheli J, Leenstra J, Guthrie GL, Nguyen DQ, Blaner B, Marino CF, Retter E, Williams P (2011) IBM POWER7 multicore server processor. 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Low Power Processor Architectures and Contemporary Techniques for Power Optimization â A Review
The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER
A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design
Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 ”W. PSpice simulation results using the 0.18 ”m CMOS technology from TSMC are included to verify the design functionality and correspondence with theory
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