A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm

We propose an optical flow processor, which allows real-Time processing of WXGA 30-fps at 178.3 MHz. By introducing the SOR method and a pipeline operation for the Gauss-Seidel method to the iterative flow calculation, computational complexity can be reduced to 14.5% when compared to the previous HOE processor. We decreased the area of the embedded memory by using the image division method, applying line memory, and optimizing the computation word length. The core size of the designed processor is 16.82 mm2 in 90 nm process technology, which is approximately 5% of the previous HOE processor. The processor can operate completely in parallel, which ensures high-resolution scalability. © 2015 IEEE. 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015; Belgrade; Serbia; 22 April 2015 through 24 April 2015; Category numberE5519; Code 11688

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding

Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....Comment: arXiv admin note: text overlap with arXiv:1704.0761

A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm

We propose an optical flow processor, which allows real-Time processing of WXGA 30-fps at 178.3 MHz. By introducing the SOR method and a pipeline operation for the Gauss-Seidel method to the iterative flow calculation, computational complexity can be reduced to 14.5% when compared to the previous HOE processor. We decreased the area of the embedded memory by using the image division method, applying line memory, and optimizing the computation word length. The core size of the designed processor is 16.82 mm2 in 90 nm process technology, which is approximately 5% of the previous HOE processor. The processor can operate completely in parallel, which ensures high-resolution scalability. © 2015 IEEE.18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015; Belgrade; Serbia; 22 April 2015 through 24 April 2015; Category numberE5519; Code 11688

Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC) technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real Delta-Sigma modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the Delta-Sigma modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits) was achieved

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory