DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

Design and characterization of downconversion mixers and the on-chip calibration techniques for monolithic direct conversion radio receivers

This thesis consists of eight publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis is focused on the design of downconversion mixers and direct conversion radio receivers for UTRA/FDD WCDMA and GSM standards. The main interest of the work is in the 1-3 GHz frequency range and in the Silicon and Silicon-Germanium BiCMOS technologies. The RF front-end, and especially the mixer, limits the performance of direct conversion architecture. The most stringent problems are involved in the second-order distortion in mixers to which special attention has been given. The work introduces calibration techniques to overcome these problems. Some design considerations for front-end radio receivers are also given through a mixer-centric approach. The work summarizes the design of several downconversion mixers. Three of the implemented mixers are integrated as the downconversion stages of larger direct conversion receiver chips. One is realized together with the LNA as an RF front-end. Also, some stand-alone structures have been characterized. Two of the mixers that are integrated together with whole analog receivers include calibration structures to improve the second-order intermodulation rejection. A theoretical mismatch analysis of the second-order distortion in the mixers is also presented in this thesis. It gives a comprehensive illustration of the second-order distortion in mixers. It also gives the relationships between the dc-offsets and high IIP2. In addition, circuit and layout techniques to improve the LO-to-RF isolation are discussed. The presented work provides insight into how the mixer immunity against the second-order distortion can be improved. The implemented calibration structures show promising performance. On the basis of these results, several methods of detecting the distortion on-chip and the possibilities of integrating the automatic on-chip calibration procedures to produce a repeatable and well-predictable receiver IIP2 are presented.reviewe

Development of a temperature insensitive current controlled current source for LNA bias circuit applications

The research described in this thesis is concerned with the analysis, design and development of a novel temperature insensitive Current Controlled Current Source (CCCS), in bipolar technology, in order to provide accurate amplification of a Proportional To Absolute Temperature (PTAT) reference current. The output current of the CCCS is intended for application as the bias current for a bipolar Low Noise Amplifier (LNA) in order to minimise gain variations with temperature across the industrial temperature range (-40·C to 8S·C). The thesis begins with an explanation of key parameters concerned with LNA design and a target specification is defined. In Chapter 2, a conventional LNA, with constant with temperature bias current, is developed following a methodical approach based on conventional techniques. This meets the previously defined specification at room temperature but exhibits large gain variations with changes in temperature. The analysis and simulation results of this conventional LNA serve as a benchmark for comparison with later designs. In order to minimise any gain variations with temperature of a bipolar amplifier it is well known that the applied bias current should be PT AT. Thus, a thorough analysis and comparative review of traditional and novel PTAT reference current generator circuits is conducted in Chapters 3 and 4. Based on these findings the PTAT generator exhibiting best performance in terms of output current accuracy and insensitivity to power supply variations is presented. However, this circuit cannot accurately produce large rnA level currents necessary for LNA bias applications so that sufficient linearity of the LNA is maintained. Thus, a need for some form of accurate CCCS or Voltage Controlled Current Source (VCCS), which should be temperature insensitive in order to preserve the desired temperature coefficient of the reference current/voltage, is highlighted. Traditional VCCS/CCCS designs are investigated in Chapter 5. Limitations of these approaches leads to the design and development ofa novel CCCS with built in PTAT reference. The presented CCCS utilises a new, previously unseen, architecture and has led to a patent application [1]. The author has reported the majority of this work in technical literature [2-4]. In Chapter 6, the output of the novel CCCS is adapted to include the conventional LNA circuit designed previously in Chapter 2. The results of the combined LNA and CCCS are compared with the conventional LNA. The combined LNA and CCCS offers a dramatic reduction in gain variation with temperature

Characteristics of UHF transistors using autoregistered structures

The basis of a novel bipolar transistor structure was proposed by Dr R. Aubusson of Middlesex Polytechnic in 1977. The novelty lies in replacing the conventional overlay transistor's P+ base grid with a refractory metal grid, in order (a) to lower the base resistance and (b) to autoregister the emitter. It was claimed that the linearity of the transistor would also be improved. A number of questions raised by this idea have been investigated, the methods and conclusions of which are presented here. Plausible structures, using the metal base grid, are proposed and compared with conventional structures. Some advantages are seen to be possible. The current understanding of distortion analysis applied to transistors is reviewed. The main ideas are presented in a unified manner and are extended to higher order. A number of the transistor's second order effects are analysed in a novel fashion. The metal base grid transistor is analysed and compared with conventional transistors, with favourable results. Practical aspects of fabricating the metal base grid transistor were investigated. A procedure for deposition has been determined and is presented here along with the film physical and electrical characteristics. Analysis of the tungsten-silicon interface shows the suitability of the metallization as a base grid. Suitable means of delineating the tungsten film have been assessed and a working procedure determined. Subsequent deposition of various insulators has been investigated and the problems associated with the readily oxidized tungsten film have been overcome. Formation of the emitter, requiring further high temperature processing, has been assessed in view of the limitations imposed by the preformed base metallization. In summary, it has been shown that the novel structure can be constructed and that significant performance improvement is to be expected, although a full realization was not possible within the resource constraints of the project

Radio frequency circuits for wireless receiver front-ends

The beginning of the 21st century sees great development and demands on wireless communication technologies. Wireless technologies, either based on a cable replacement or on a networked environment, penetrate our daily life more rapidly than ever. Low operational power, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver??s front-end circuits play an important role in faithfully recovering the information transmitted through the wireless channel. Bluetooth is a short-range cable replacement wireless technology. A Bluetooth receiver architecture was proposed and designed using a pure CMOS process. The front-end of the receiver consists of a low noise amplifier (LNA) and mixer. The intermediate frequency was chosen to be 2MHz to save battery power and alleviate the low frequency noise problem. A conventional LNA architecture was used for reliability. The mixer is a modified Gilbert-cell using the current bleeding technique to further reduce the low frequency noise. The front-end draws 10 mA current from a 3 V power supply, has a 8.5 dB noise figure, and a voltage gain of 25 dB and -9 dBm IIP3. A front-end for dual-mode receiver is also designed to explore the capability of a multi-standard application. The two standards are IEEE 802.11b and Bluetooth. They work together making the wireless experience more exciting. The front-end is designed using BiCMOS technology and incorporating a direct conversion receiver architecture. A number of circuit techniques are used in the front-end design to achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a 5.5 dB noise figure, 33 dB voltage gain and -13 dBm IIP3. Besides the system level contributions, intensive studies were carried out on the development of quality LNA circuits. Based on the multi-gated LNA structure, a CMOS LNA structure using bipolar transistors to provide linearization is proposed. This LNA configuration can achieve comparable linearity to its CMOS multi-gated counterpart and work at a higher frequency with less power consumption. A LNA using an on-chip transformer source degeneration is proposed to realize input impedance matching. The possibility of a dual-band cellular application is studied. Finally, a study on ultra-wide band (UWB) LNA implementation is performed to explore the possibility and capability of CMOS technology on the latest UWB standard for multimedia applications

High Efficiency Design Techniques for Linear Power Amplifiers

abstract: This thesis describes the design process used in the creation of a two stage cellular power amplifier. A background for understanding amplifier linearity, device properties, and ACLR estimation is provided. An outline of the design goals is given with a focus on linearity with high efficiency. The full design is broken into smaller elements which are discussed in detail. The main contribution of this thesis is the description of a novel interstage matching network topology for increasing efficiency. Ultimately the full amplifier design is simulated and compared to the measured results and design goals. It was concluded that the design was successful, and used in a commercially available product.Dissertation/ThesisM.S. Electrical Engineering 201

Design and Characterization of Circuits for Next-Generation Wireless Communications Systems

Demand for wireless data transfer has been increasing rapidly with the rise of smart devices and mobile video streaming. With dozens of wireless applications currently in use and only a finite bandwidth to work with, engineers are challenged to both expand the upward frequency limit of high-performance, high-efficiency wireless systems and to increase the spectral efficiency of the frequency bands already in use. The development of deep sub-um silicon-on-insulator transistor technology and powerful computer-aided circuit designing tools have allowed us to create more affordable silicon-based phased array ICs at frequencies previously achievable by only military applications. The 5th generation of mobile systems (5G) is now expected to use this type of IC to offer increased wireless data capacity in densely-populated areas using mm-wave frequencies. Demand for wireless data is only expected to continue rising, particularly as new IoT applications such as autonomous vehicles become commercially viable.The work presented in this dissertation addresses both the need for expanding the usable frequency spectrum and the need to increase spectral efficiency in available bands. It includes a design for an analog beamforming matrix for a spatially multiplexed phased array receiver in silicon SOI technology, low-power high-linearity w-band amplifiers in InP HBT technology, and ultra-wideband mm-wave power amplifiers in InP HBT technology. Spatially multiplexed phased array transceivers have the potential to greatly increase the spectral efficiency of mm-wave frequency bands by re-using frequency spectrum for many data channels. This type of system can be used to create short-range high-capacity line-of-sight wireless backhaul for crowded city squares or event venues. Mm-wave power amplifiers and high-linearity amplifiers in new 130 nm InP HBT technology represent an IC performance boost which pushes the frequency limits of feasible power-efficient wireless systems. The measured power amplifier ICs produce output power of larger than 16.5 dBm at the 3-dB gain compression condition from 50 GHz to 100 GHz, and a small signal gain of 15 dB over a 90 GHz 3-dB bandwidth. The peak power-added efficiency (PAE) is larger than 8% over that same frequency range. At 90 GHz, the ICs produce 22 dBm of saturated output power and 14.7% PAE. The measured high-linearity amplifier ICs demonstrate an output-referred 3rd order intercept (OIP3) of 22 dBm, a gain of 6.4 dB, and a noise figure below 7 dB at 100 GHz. New designs for an analog MIMO beamforming matrix IC, a 100-165 GHz power amplifier, and an improved w-band high-linearity amplifier are also outlined in this dissertation