Reversible computation, a quantum-inspired low-consumption viable technology?

Through the very last reversible CMOS circuit realizations, this tutorial will discuss the viability of the quantuminspired low-consumption reversible pass-transistor CMOS technology

Energy consumption by reversible circuits in the 130 nm and 65 nm nodes

We show that both 130 nm and 65 nm technologies are suitable for reversible computation

A technology based complexity model for reversible Cuccaro ripple-carry adder

Reversible logic provides an alternative to classical computing, that may overcome many of the power dissipation problems. The paper presents a simple complexity model, from the study of a cascade of Cuccaro adders processed in standard 0.35 micrometer CMOS technology

Interfacing reversible pass-transistor CMOS chips with conventional restoring CMOS circuits

Important progress has been made recently in the prototyping of reversible (quantum) digital circuits, proving that digital reversible dual-line pass-transistor technology may be used for applications in reversible linear computation. This raises new questions regarding the compatibility of this new technology with existing standard switching CMOS technology. The greatest difficulty is brought by the difference of signal shape used by the two technologies. Whereas standard switching CMOS circuits make use of rectangular pulses, dual-line pass-transistor reversible circuits use adiabatic triangular or trapezoidal ones. This work proposes a simple technical solution that allows interfacing digital reversible pass-transistor with conventional CMOS switching technology represented here by a Xilinx FPGA embedded on a commercial Spartan-3E board. All the proposed solutions have successfully been tested, allowing the FPGA to practically drive a reversible chip