A design representation model for high-level synthesis

Design tools share and exchange various types of information pertaining to the design. The identification of a uniform design representation to capture this information is essential for the development of a successful design environment. We have done an extensive study on the representation needs of existing database tools in the UCI CADLAB; examples of which are graph compilers for high-level hardware specifications, state schedulers, hardware allocators, and microarchitecture optimizers. The result of this study is the development of a design representation model that will serve as a common internal representation (DDM) for all system and behavioral synthesis tools. DDM thus builds the foundation for a CAD Framework in which design tools can communicate via operating on this common representation. The design information is composed of three separate graph models: the conceptual model, the behavioral model and the structural model. The conceptual model (represented by a Design Entity Graph) captures the overall organization of the design information, such as, versions and configurations. The behavioral model (represented by an Augmented Control/Data Flow Graph) describes the design behavior. The structural model (represented by an Annotated Component Graph) captures the hierarchical data path structure and its geometric information. In this paper, we define the last two graph models. They both capture the actual design data of the application domain. Since VHDL has gained increasing popularity as hardware description language for synthesis, we give numerous examples throughout this report that show how the proposed design representation model can be used to represent VHDL specifications

Chippe : a system for constraint driven behavioral synthesis

This report describes the Chippe system, gives some background previous work and describes several sample design runs of the system. Also presented are the sources of the design tradeoffs used by Chippe, and overview of the internal design model, and experiences using the system

An Overview of Integral Quadratic Constraints for Delayed Nonlinear and Parameter-Varying Systems

A general framework is presented for analyzing the stability and performance of nonlinear and linear parameter varying (LPV) time delayed systems. First, the input/output behavior of the time delay operator is bounded in the frequency domain by integral quadratic constraints (IQCs). A constant delay is a linear, time-invariant system and this leads to a simple, intuitive interpretation for these frequency domain constraints. This simple interpretation is used to derive new IQCs for both constant and varying delays. Second, the performance of nonlinear and LPV delayed systems is bounded using dissipation inequalities that incorporate IQCs. This step makes use of recent results that show, under mild technical conditions, that an IQC has an equivalent representation as a finite-horizon time-domain constraint. Numerical examples are provided to demonstrate the effectiveness of the method for both class of systems

Robust nonlinear control of vectored thrust aircraft

An interdisciplinary program in robust control for nonlinear systems with applications to a variety of engineering problems is outlined. Major emphasis will be placed on flight control, with both experimental and analytical studies. This program builds on recent new results in control theory for stability, stabilization, robust stability, robust performance, synthesis, and model reduction in a unified framework using Linear Fractional Transformations (LFT's), Linear Matrix Inequalities (LMI's), and the structured singular value micron. Most of these new advances have been accomplished by the Caltech controls group independently or in collaboration with researchers in other institutions. These recent results offer a new and remarkably unified framework for all aspects of robust control, but what is particularly important for this program is that they also have important implications for system identification and control of nonlinear systems. This combines well with Caltech's expertise in nonlinear control theory, both in geometric methods and methods for systems with constraints and saturations

Robust Scale-Free Synthesis for Frequency Control in Power Systems

The AC frequency in electrical power systems is conventionally regulated by synchronous machines. The gradual replacement of these machines by asynchronous renewable-based generation, which provides little or no frequency control, increases system uncertainty and the risk of instability. This imposes hard limits on the proportion of renewables that can be integrated into the system. In this paper we address this issue by developing a framework for performing frequency control in power systems with arbitrary mixes of conventional and renewable generation. Our approach is based on a robust stability criterion that can be used to guarantee the stability of a full power system model on the basis of a set of decentralised tests, one for each component in the system. It can be applied even when using detailed heterogeneous component models, and can be verified using several standard frequency response, state-space, and circuit theoretic analysis tools. Furthermore the stability guarantees hold independently of the operating point, and remain valid even as components are added to and removed from the grid. By designing decentralised controllers for individual components to meet these decentralised tests, every component can contribute to the regulation of the system frequency in a simple and provable manner. Notably, our framework certifies the stability of several existing (non-passive) power system control schemes and models, and allows for the study of robustness with respect to delays.Comment: 10 pages, submitte

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

CLEX: Yet Another Supercomputer Architecture?

We propose the CLEX supercomputer topology and routing scheme. We prove that CLEX can utilize a constant fraction of the total bandwidth for point-to-point communication, at delays proportional to the sum of the number of intermediate hops and the maximum physical distance between any two nodes. Moreover, % applying an asymmetric bandwidth assignment to the links, all-to-all communication can be realized $(1+o(1))$-optimally both with regard to bandwidth and delays. This is achieved at node degrees of $n^{\varepsilon}$, for an arbitrary small constant $\varepsilon\in (0,1]$. In contrast, these results are impossible in any network featuring constant or polylogarithmic node degrees. Through simulation, we assess the benefits of an implementation of the proposed communication strategy. Our results indicate that, for a million processors, CLEX can increase bandwidth utilization and reduce average routing path length by at least factors $10$ respectively $5$ in comparison to a torus network. Furthermore, the CLEX communication scheme features several other properties, such as deadlock-freedom, inherent fault-tolerance, and canonical partition into smaller subsystems