A high power CMOS class-D amplifier for inductive-link medical transmitters

Powering of medical implants by inductive coupling is an effective technique, which avoids the use of bulky implanted batteries or transcutaneous wires. On the external unit side, class-D and class-E power amplifiers (PAs) are conventionally used thanks to their high efficiency at high frequencies. The initial specifications driving this work require the use of multiple independent stimulators, which imposes serious constraints on the area and functionality of the external unit. An integrated circuit class-D PA has been designed to provide both small area and enhanced functionality, the latter achieved by the addition of an on-chip phased-locked loop (PLL), a dead-time generator and a phase detector. The PA has been designed in a 0.18μm CMOS high-voltage process technology and occupies an area of 9.86 mm2. It works at frequencies up to 14 MHz and 30 V supply and efficiencies higher than 80% are obtained at 14 MHz. The PA is intended for a closed-loop transmitter system that optimises power delivery to medical implants

Micromechanical tuning elements in a 620-GHz monolithic integrated circuit

While monolithic integrated-circuit technology promises a practical means for realizing reliable reproducible planar millimeter and submillimeter-wave circuits, conventional planar circuits do not allow for critical post-fabrication optimization of performance. A 620-GHz quasi-optical monolithic detector circuit is used here to demonstrate the performance of two integrated micromechanical planar tuning elements. This is the first reported demonstration of integrated micromechanical tuning at submillimeter wavelengths. The tuning elements, called sliding planar backshorts (SPBs), are used to adjust the electrical length of planar transmission-line tuning stubs to vary the power delivered between a substrate-lens coupled planar antenna and a thin-film bismuth detector over a range of nearly 15 dB. The circuit performance agrees with theoretical calculations and microwave measurements of a -0.06-dB reflection coefficient made for a scale model of the integrated tuners. The demonstrated tuning range for the SPB tuners indicates that they can be valuable for characterizing components in developmental circuits and for optimizing the in-use performance of various millimeter and submillimeter-wave integrated circuits

Rectification, amplification and switching capabilities for energy harvesting systems: power management circuit for piezoelectric energy harvester

Dissertação de mestrado em Biomedical EngineeringA new energy mechanism needs to be addressed to overcome the battery dependency, and consequently extend Wireless Sensor Nodes (WSN) lifetime effectively. Energy Harvesting is a promising technology that can fulfill that premise. This work consists of the realization of circuit components employable in a management system for a piezoelectric-based energy harvester, with low power consumption and high efficiency. The implementation of energy harvesting systems is necessary to power-up front-end applications without any battery. The input power and voltage levels generated by the piezoelectric transducer are relatively low, especially in small-scale systems, as such extra care has to be taken in power consumption and efficiency of the circuits. The main contribution of this work is a system capable of amplifying, rectifying and switching the unstable signal from an energy harvester source. The circuit components are designed based on 0.13 Complementary Metal-Oxide-Semiconductor (CMOS) technology. An analog switch, capable of driving the harvesting circuit at a frequency between 1 and 1 , with proper temperature behaviour, is designed and verified. An OFF resistance of 520.6 Ω and isolation of −111.24 , grant excellent isolation to the circuit. The designed voltage amplifier is capable of amplifying a minor signal with a gain of 42.56 , while requiring low power consumption. The output signal is satisfactorily amplified with a reduced offset voltage of 8 . A new architecture of a two-stage active rectifier is proposed. The power conversion efficiency is 40.4%, with a voltage efficiency of up to 90%. Low power consumption of 17.7 is achieved by the rectifier, with the embedded comparator consuming 113.9 . The outcomes validate the circuit’s power demands, which can be used for other similar applications in biomedical, industrial, and commercial fields.Para combater a dependência dos dispositivos eletrónicos relativamente ás baterias é necessário um novo sistema energético, que permita prolongar o tempo de vida útil dos mesmos. Energy Harvesting é uma tecnologia promissora utilizada para alimentar dispositivos sem bateria. Este trabalho consiste na realização de componentes empregáveis num circuito global para extrair energia a partir ds vibrações de um piezoelétricos com baixo consumo de energia e alta eficiência. Os níveis de potência e voltagem gerados pelo transdutor piezoelétrico são relativamente baixos, especialmente em sistemas de pequena escala, por isso requerem cuidado extra relativamente ao consumo de energia e eficiência dos circuitos. A principal contribuição deste trabalho é um sistema apropriado para amplificar, retificar e alternar o sinal instável proveniente de uma fonte de energy harvesting. Os componentes do sistema são implementados com base na tecnologia CMOS com 0.13 . Um interruptor analógico capaz de modelar a frequência do sinal entre 1 e 1 e estável perante variações de temperatura, é implementado. O circuito tem um excelente isolamento de −111.24 , devido a uma resistência OFF de 520.6 Ω. O amplificador implementado é apto a amplificar um pequeno sinal com um ganho de 42.56 e baixo consumo. O sinal de saída é satisfatoriamente amplificado com uma voltagem de offset de 8 . Um retificador ativo de dois estágios com uma nova arquitetura é proposto. A eficiência de conversão de energia atinge os 40.4%, com uma eficiência de voltagem até 90%. O retificador consome pouca energia, apenas 17.7 , incorporando um comparador de 113.9 . Os resultados validam as exigências energéticas do circuito, que pode ser usado para outras aplicações similares no campo biomédico, industrial e comercial

Hardware design of LIF with Latency neuron model with memristive STDP synapses

In this paper, the hardware implementation of a neuromorphic system is presented. This system is composed of a Leaky Integrate-and-Fire with Latency (LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL neuron model allows to encode more information than the common Integrate-and-Fire models, typically considered for neuromorphic implementations. In our system LIFL neuron is implemented using CMOS circuits while memristor is used for the implementation of the STDP synapse. A description of the entire circuit is provided. Finally, the capabilities of the proposed architecture have been evaluated by simulating a motif composed of three neurons and two synapses. The simulation results confirm the validity of the proposed system and its suitability for the design of more complex spiking neural network

Index to 1981 NASA Tech Briefs, volume 6, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1981 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Small Radioisotope Power System at NASA Glenn Research Center

In April 2009, NASA Glenn Research Center (GRC) formed an integrated product team (IPT) to develop a Small Radioisotope Power System (SRPS) utilizing a single Advanced Stirling Convertor (ASC) with passive balancer for possible use by the International Lunar Network (ILN) program. The ILN program is studying the feasibility of implementing a multiple node seismometer network to investigate the internal lunar structure. A single ASC produces approximately 80 W(sub e) and could potentially supply sufficient power for that application. The IPT consists of Sunpower, Inc., to provide the single ASC with balancer, The Johns Hopkins University Applied Physics Laboratory (JHU/APL) to design an engineering model Single Convertor Controller (SCC) for an ASC with balancer, and NASA GRC to provide technical support to these tasks and to develop a simulated lunar lander test stand. A controller maintains stable operation of an ASC. It regulates the alternating current produced by the linear alternator of the convertor, provides a specified output voltage, and maintains operation at a steady piston amplitude and hot end temperature. JHU/APL also designed an ASC dynamic engine/alternator simulator to aid in the testing and troubleshooting of the SCC. This paper describes the requirements, design, and development of the SCC, including some of the key challenges and the solutions chosen to overcome those issues. In addition, it describes the plans to analyze the effectiveness of a passive balancer to minimize vibration from the ASC, characterize the effect of ASC vibration on a lunar lander, characterize the performance of the SCC, and integrate the single ASC, SCC, and lunar lander test stand to characterize performance of the overall system

A Modular Multi-level Converter for Energy Management of Hybrid Energy-Storage Systems in Electric Vehicles

Electric vehicles (EVs) are substantial applications of clean energy. Their effectiveness for mainstream transportation is predicated on the efficient use of stored energy within the vehicles’ power pack. Among rechargeable storage solutions, lithium-ion (Li-ion) battery cells have high energy density making them suitable to supply the EVs’ average power. However, the peak power requirements of the vehicles exert stress on the Li-ion cells due to their low pulsating power capabilities. Ultracapacitors can be used instead as the power-pulsating storage elements given their superior power density. Incorporating the two cell types for energy storage signifies a hybrid configuration that leads to challenging tasks in managing the energy between cells due to varying cell dynamics. Therefore, this study investigated the design of an end-to-end hybrid energy-storage and management system. The limitations of existing power electronics and control schemes were identified based on comparative analysis, both on a cell level and on a system level. Subsequently, an energy system was developed that utilized modular multi-level converters to manage the energy between the different cell types. The formulated control strategy accounted for various power modes and added immense flexibility in charge sharing through diverse switching states. Furthermore, the proposed configuration eliminated the conventional need for a system level drive inverter feeding the EV motor. Electro-mechanical modeling results and physical design merits verified the proposed configuration’s effectiveness in improving EV efficiency

RF Controlled Robotic Vehicle with Metal Detection Project

The project is intended to cultivate a robotic vehicle that can sense metals ahead of it on its path similar to detecting land mines. The robot is controlled by a remote using RF technology. It consists of a metal detector circuit interfaced to the control unit that alarms the user behind it about a doubted land mine ahead. An 8051 series of microcontroller is used for the preferred operation. For controlling the movement of robot either to forward, backward & right or left commands are sent to the receiver by using push buttons of the transmitter. At the receiving end two motors are interfaced to the microcontroller where they are used for the movement of the vehicle. The RF transmitter acts as a RF remote control that has the advantage of sufficient range (up to 200 meters) with proper antenna, while the receiver decodes before serving it to another microcontroller to drive DC motors via motor driver IC for necessary work. A metal detector circuit is attached on the robot body and its operation is carried out automatically on sensing any metal underneath. The instant the robot senses this metal it produces an alarm sound through buzzer. This is to aware the operator of a probable metal (eg: land mine) ahead on its path. Further the project can be enhanced by mounting a wireless camera on the robot so that the operator can govern the movement of the robot remotely by observing it on a screen

MFPA: Mixed-Signal Field Programmable Array for Energy-Aware Compressive Signal Processing

Compressive Sensing (CS) is a signal processing technique which reduces the number of samples taken per frame to decrease energy, storage, and data transmission overheads, as well as reducing time taken for data acquisition in time-critical applications. The tradeoff in such an approach is increased complexity of signal reconstruction. While several algorithms have been developed for CS signal reconstruction, hardware implementation of these algorithms is still an area of active research. Prior work has sought to utilize parallelism available in reconstruction algorithms to minimize hardware overheads; however, such approaches are limited by the underlying limitations in CMOS technology. Herein, the MFPA (Mixed-signal Field Programmable Array) approach is presented as a hybrid spin-CMOS reconfigurable fabric specifically designed for implementation of CS data sampling and signal reconstruction. The resulting fabric consists of 1) slice-organized analog blocks providing amplifiers, transistors, capacitors, and Magnetic Tunnel Junctions (MTJs) which are configurable to achieving square/square root operations required for calculating vector norms, 2) digital functional blocks which feature 6-input clockless lookup tables for computation of matrix inverse, and 3) an MRAM-based nonvolatile crossbar array for carrying out low-energy matrix-vector multiplication operations. The various functional blocks are connected via a global interconnect and spin-based analog-to-digital converters. Simulation results demonstrate significant energy and area benefits compared to equivalent CMOS digital implementations for each of the functional blocks used: this includes an 80% reduction in energy and 97% reduction in transistor count for the nonvolatile crossbar array, 80% standby power reduction and 25% reduced area footprint for the clockless lookup tables, and roughly 97% reduction in transistor count for a multiplier built using components from the analog blocks. Moreover, the proposed fabric yields 77% energy reduction compared to CMOS when used to implement CS reconstruction, in addition to latency improvements