A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

Design of reconfigurable multi-mode RF circuits

Wireless communication systems and devices have been developing at a much faster pace in the past few years. With the introduction of new applications and services and the increasing demand for higher data rate comes the need for new frequency bands and new standards. One critical issue for next generation wireless devices is how to support all of the existing and emerging bands while not increasing the cost and power consumption. A feasible solution is the concept of the software-defined radio where a single receiver can be reconfigured to operate in different modes, each of which supports one or several bands and/or standards. To implement such a reconfigurable receiver, reconfigurable RF building blocks, such as the LNA, mixer, VCO, etc., are required. This dissertation focuses on two key blocks: the low noise amplifier (LNA) and the voltage controlled oscillator (VCO). First the design, modeling and characterization of a multi-tap transformer are discussed. Simple mathematical calculations are utilized to estimate the inductances and coupling coefficients from the physical parameters of a multi-tap transformer. The design method is verified with several designed multi-tap transformers that are characterized up to 10 GHz using Momentum simulation results. The effect of switch loss on a switched multi-tap transformer is explored and a broadband lumped-element model of the multi-tap transformer is also proposed. Next a reconfigurable multimode LNA capable of single-band, concurrent dual-band, and ultra-wideband operation is presented. The multimode operation is realized by incorporating a switched multi-tap transformer into the input matching network of an inductively degenerated common source amplifier. The proposed LNA achieves single band matching at 2.8, 3.3, and 4.6 GHz; concurrent dual-band matching at 2.05 and 5.65 GHz; and ultra-wideband matching from 4.3 to 10.8 GHz. The chip was fabricated in a 0.13 m CMOS process, and occupies an area of 0.72 mm2, and has a power dissipation of 6.4 mW from a 1.2-V supply. Finally, a triple-mode VCO using a transformer-based 4th order tank with tunable transconductance cells coupling the primary and secondary inductor is introduced. The tank impedance can be re-shaped by the transconductance cells through the tuning of their biasing currents. With the control of biasing current, VCO is configured in three modes, capable of generating a single frequency in 3- and 5- GHz bands, respectively, and two frequencies in both 3- and 5- GHz bands simultaneously. The triple-mode VCO was fabricated in a 0.13 μm CMOS process, occupies an area of 0.16 mm2, and dissipates 5.6 mW from a 1.2-V supply

Design of a 4.2-5.4 GHz differential LC VCO using 0.35 mu m SiGeBiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2-5.4 GHz, -Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 mu m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is -110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and -113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm(2) on Si substrate, including DC and RF pads

Design of a Magnetically Tunable Low Noise Amplifier in 0.13 um CMOS Technology

With legacy technologies present and approaching new wireless standards, the 1-10 GHz band of frequencies is quickly becoming saturated. Although saturated, the frequency bands are being utilized inefficiently. Cognitive radio, an intelligent wireless communication system, is the novel solution for the efficient utilization of the frequency bands. Front-end receivers for cognitive radio will need the capability to receive and process multiple frequency bands and a key component is the low noise amplifier (LNA). A tunable LNA using a new magnetically tuned input impedance matching network is presented. The LNA has been designed and simulated in a commercially available 0.13 μm CMOS technology and is capable of tuning from 3.2 GHz to 4.6 GHz as S11 \u3c -10 dB. Within this bandwidth the maximum power gain is 16.2 dB, the maximum noise figure is 7.5 dB, and the minimum IIP3 is -6.4 dBm. The total power consumption of the LNA (neglecting the buffer required to drive the 50 Ω test equipment) is 50 mW. This tunable LNA introduces a new magnetically tunable matching technique and tuning scheme capable of continuous frequency variation for LNAs. It is expected that this technique could be expanded to realize LNAs with a tunable, narrow-band response that can cover the entire 1-10 GHz band of frequencies. The presented tunable LNA has demonstrated the capability to cover and process multiple frequencies and can be used for reconfigurable systems. A tunable LNA design is the first step in an effort to realize a fully reconfigurable front-end radio frequency (RF) receiver for future cognitive radio applications

Ultra-wideband CMOS signal generator using tunable linear superposition

Department of Electrical EngineeringWireless communication frequency bandwidth and center frequency are have been widening for high speed transmission of data. But the frequency bandwidth a transceiver can cover is severely limited. The circuit designed in the paper, called "signal generator", can offer a variety of wireless bandwidths. In this paper, a ultra wideband signal generator, based in 65nm CMOS technology, is designed after proposing and verifying two different types of signal generator design. The first version design of the signal generator is proposed, which is composed of a four-stage LC-ring voltagecontrolled oscillator (VCO) and a frequency synthesis circuit. A new concept of tunable linear superposition is proposed for wideband frequency synthesis and implemented to provide VCO core (1X)/ twofold (2X)/ quadruple (4X) programmable frequency multiplication function. In order to expand frequency coverage further, the LCring VCO adopted the tunable inductors which are composed of switchable bondwire pairs. A ultra-wideband operation from 4.3GHz to 27.4GHz was experimentally verified. The second version design of the signal generator using a reconfigurable phase selection process is proposed, which is proposed and consists of a multi-phase signal generation and a programmable frequency multiplication. This chip is proposed for wideband frequency synthesis and implemented to provide VCO core (1X)/ twofold (2X)/ quadruple (4X) and octuplet (8X) programmable frequency multiplication function. An LC-ring oscillator and a selective rectifying combiner are reconstructed adaptively for various frequency synthesis modes, minimizing their power consumption. A fully-integrated prototype verified to have very wide frequency characteristic from 6.3GHz to 59.4GHz.ope

Mixed-Domain Fast Simulation of RF and Microwave MEMS-based Complex Networks within Standard IC Development Frameworks

MS technology (MicroElectroMechanical-System) has been successfully employed since a few decades in the sensors/actuators field. Several products available on the market nowadays include MEMS-based accelerometers and gyroscopes, pressure sensors and micro-mirrors matrices. Beside such well-established exploitation of MEMS technology, its use within RF (Radio Frequency) blocks and systems/sub-systems has been attracting, in recent years, the interest of the Scientific Community for the significant RF performances boosting that MEMS devices can enable. Several significant demonstrators of entirely MEMS-based lumped components, like variable capacitors (Hyung et al., 2008), inductors (Zine-El-Abidine et al., 2003) and micro-switches (Goldsmith et al., 1998), are reported in literature, exhibiting remarkable performance in terms of large tuning-range, very high Q-Factor and low-loss, if compared with the currently used components implemented in standard semiconductor technology (Etxeberria & Gracia, 2007, Rebeiz & Muldavin, 1999). Starting from the just mentioned basic lumped components, it is possible to synthesize entire functional sub-blocks for RF applications in MEMS technology. Also in this case, highly significant demonstrators are reported and discussed in literature concerning, for example, tuneable phase shifters (Topalli et al., 2008), switching matrices (Daneshmand & Mansour, 2007), reconfigurable impedance matching networks (Larcher et al., 2009) and power attenuators (Iannacci et al., 2009, a). In all the just listed cases, the good characteristics of RF-MEMS devices lead, on one side, to very highperformance networks and, on the other hand, to enabling a large reconfigurability of the entire RF/Microwave systems employing MEMS sub-blocks. In particular, the latter feature addresses two important points, namely, the reduction of hardware redundancy, being for instance the same Power Amplifier within a mobile phone suitable both in transmission (Tx) and reception (Rx) (De Los Santos, 2002), and the usability of the same RF apparatus in compliance with different communication standards (like GSM, UMTS, WLAN and so on) (Varadan, 2003). Beside the exploitation of MEMS technology within RF transceivers, other potentially successful uses of Microsystems are in the Microwave field, concerning, e.g., very compact switching units, especially appealing to satellite applications for the very reduced weight (Chung et al., 2007), and phase shifters in order to electronically steer short and mid-range radar systems for the homeland security and monitoring applications (Maciel et al., 2007). Given all the examples reported above, it is straightforward that the employment of a proper strategy in aiming at the RF-MEMS devices/networks optimum design is a key-issue in order to gain the best benefits, in terms of performance, that such technology enables to address. This is not an easy task as the behaviour of RF-MEMS transversally crosses different physical domains, namely, electrical, mechanical and electromagnetic, leading to a large number of trade-offs between mechanical and electrical/electromagnetic parameters, that typically cannot be managed within a unique commercial simulation tool. In this chapter, a complete approach for the fast simulation of single RF-MEMS devices as well as of complex networks is presented and discussed in details. The proposed method is based on a MEMS compact model library, previously developed by the author, within a commercial simulation environment for ICs (integrated circuits). Such software tool describes the electromechanical mixed-domain behaviour typical of MEMS devices. Moreover, through the chapter, the electromagnetic characteristics of RF-MEMS will be also addressed by means of extracted lumped element networks, enabling the whole electromechanical and electromagnetic design optimization of the RF-MEMS device or network of interest. In particular, significant examples about how to acc..

Wideband 0.18µm CMOS VCO Using Active Inductor with Negative Resistance

This paper presents a wideband voltage controlled oscillator topology based on an active inductor generating negative resistance. The proposed architecture covers a frequency band between 1.325 GHz - 2.15 GHz with average in-band phase noise of -86 dBc/Hz at 1 MHz offset from the carrier frequency. Power consumption of the oscillator core is 28 mW from a 1.8 V supply. The circuit has been simulated in Eldo RF (Design Architect IC, Mentor Graphics) using UMC 0.18 µm 1P6M Salicide RF CMOS model libraries

Wideband 0.18µm CMOS VCO Using Active Inductor with Negative Resistance

This paper presents a wideband voltage controlled oscillator topology based on an active inductor generating negative resistance. The proposed architecture covers a frequency band between 1.325 GHz - 2.15 GHz with average in-band phase noise of -86 dBc/Hz at 1 MHz offset from the carrier frequency. Power consumption of the oscillator core is 28 mW from a 1.8 V supply. The circuit has been simulated in Eldo RF (Design Architect IC, Mentor Graphics) using UMC 0.18 µm 1P6M Salicide RF CMOS model libraries