VAI TRÒ VÀ THIẾT KẾ KHÁC NHAU CỦA ĐIỆN MÔI CỰC CỔNG DỊ CẤU TRÚC TRONG CÁC TRANSISTOR HIỆU ỨNG TRƯỜNG XUYÊN HẦM ĐƠN VÀ LƯỠNG CỔNG

Hetero-gate dielectric (HGD) engineering not only suppresses the ambipolar current but also enhances the on-current of tunnel field-effect transistors (TFETs). Based on two-dimensional device simulations, we examined the roles and designs of hetero-gate dielectric structure in single- and double-gate TFETs. Proper comparisons and analyses show that the roles and designs of source-side dielectric heterojunctions are similar, whereas those of drain-side dielectric heterojunctions are extremely different in single- and double-gate TFETs. For both device structures, the optimal position of a source-side dielectric heterojunction does not depend on the ratio of low/high-k equivalent oxide thicknesses (EOTs). When increasing the EOT ratio, the on-current enhancement by an optimized source-side dielectric heterojunction is first increased (EOT ratio < 12) and then saturated (EOT ratio > 12). The role of a drain-side dielectric heterojunction in enhancing on-current is limited in double-gate TFETs (every EOT ratio), but significant in single-gate devices (EOT ratio < 12). For EOT ratios < 12, the optimal position of a drain-side dielectric heterojunction in double-gate TFETs is around 2-3 nm farther from the source compared to that in single-gate TFETs. For EOT ratios > 12, the optimal position of a drain-side dielectric heterojunction in double-gate TFETs is not dependent on the EOT ratio, unlike single-gate TFETs. Those differences are due to the difference in the depths of local potential wells in the two TFET structures.Kỹ thuật điện môi cực cổng dị cấu trúc không chỉ giúp giảm dòng lưỡng cực mà còn làm tăng dòng mở của transistor trường xuyên hầm (tunnel field-effect transistr (TFET)). Dựa trên mô phỏng hai chiều, chúng tôi nghiên cứu vai trò và thiết kế của lớp điện môi dị cấu trúc trong TFET đơn và lưỡng cổng. Kết quả cho thấy vai trò và thiết kế của chuyển tiếp điện môi dị cấu trúc phía nguồn trong TFET đơn và lưỡng cổng hầu như giống nhau. Tuy nhiên, vai trò và thiết kế của chuyển tiếp điện môi dị cấu trúc phía máng rất khác nhau trong TFET đơn và lưỡng cổng. Trong cả hai cấu trúc, vị trí tối ưu của chuyển tiếp phía nguồn không phụ thuộc vào tỉ số bề dày ô-xít tương đương của các lớp điện môi có độ điện thẩm cao và thấp. Khi tăng tỉ số này, sự tăng dòng mở nhờ chuyển tiếp phía nguồn đầu tiên tăng (tỉ số < 12) và rồi bão hòa (tỉ số > 12). Đối với chuyển tiếp phía máng, vai trò của nó trong việc tăng dòng mở rất hạn chế trong TFET lưỡng cổng (mọi tỉ số) nhưng lại lớn trong TFET đơn cổng (tỉ số < 12). Khi tỉ số < 12, vị trí tối ưu của chuyển tiếp phía máng trong TFET lưỡng cổng xa cực nguồn hơn 2-3 nm so với trong TFET đơn cổng. Khi tỉ số > 12, vị trí tối ưu của chuyển tiếp phía máng trong TFET lưỡng cổng không phụ thuộc vào tỉ số này, nhưng trong TFET đơn cổng lại phụ thuộc. Những khác biệt trên là do các giếng thế định xứ trong hai cấu trúc có độ sâu khác nhau

A review of selected topics in physics based modeling for tunnel field-effect transistors

The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field

Core-Shell homojunction silicon vertical nanowire tunneling field-effect transistors

We propose three-terminal core-shell (CS) silicon vertical nanowire tunneling field-effect transistors (TFETs), which can be fabricated by conventional CMOS technology. CS TFETs show lower subthreshold swing (SS) and higher on-state current than conventional TFETs through their high surface-to-volume ratio, which increases carrier-tunneling region with no additional device area. The on-state current can be enhanced by increasing the nanowire height, decreasing equivalent oxide thickness (EOT) or creating a nanowire array. The off-state current is also manageable for power saving through selective epitaxial growth at the top-side nanowire region. CS TFETs with an EOT of 0.8 nm and an aspect ratio of 20 for the core nanowire region provide the largest drain current ranges with point SS values below 60 mV/dec and superior on/off current ratio under all operation voltages of 0.5, 0.7, and 1.0 V. These devices are promising for low-power applications at low fabrication cost and high device density.1130Ysciescopu

Sub-10nm Transistors for Low Power Computing: Tunnel FETs and Negative Capacitance FETs

One of the major roadblocks in the continued scaling of standard CMOS technology is its alarmingly high leakage power consumption. Although circuit and system level methods can be employed to reduce power, the fundamental limit in the overall energy efficiency of a system is still rooted in the MOSFET operating principle: an injection of thermally distributed carriers, which does not allow subthreshold swing (SS) lower than 60mV/dec at room temperature. Recently, a new class of steep-slope devices like Tunnel FETs (TFETs) and Negative-Capacitance FETs (NCFETs) have garnered intense interest due to their ability to surpass the 60mV/dec limit on SS at room temperature. The focus of this research is on the simulation and design of TFETs and NCFETs for ultra-low power logic and memory applications. Using full band quantum mechanical model within the Non-Equilibrium Greens Function (NEGF) formalism, source-underlapping has been proposed as an effective technique to lower the SS in GaSb-InAs TFETs. Band-tail states, associated with heavy source doping, are shown to significantly degrade the SS in TFETs from their ideal value. To solve this problem, undoped source GaSb-InAs TFET in an i-i-n configuration is proposed. A detailed circuit-to-system level evaluation is performed to investigate the circuit level metrics of the proposed devices. To demonstrate their potential in a memory application, a 4T gain cell (GC) is proposed, which utilizes the low-leakage and enhanced drain capacitance of TFETs to realize a robust and long retention time GC embedded-DRAMs. The device/circuit/system level evaluation of proposed TFETs demonstrates their potential for low power digital applications. The second part of the thesis focuses on the design space exploration of hysteresis-free Negative Capacitance FETs (NCFETs). A cross-architecture analysis using HfZrOx ferroelectric (FE-HZO) integrated on bulk MOSFET, fully-depleted SOI-FETs, and sub-10nm FinFETs shows that FDSOI and FinFET configurations greatly benefit the NCFET performance due to their undoped body and improved gate-control which enables better capacitance matching with the ferroelectric. A low voltage NC-FinFET operating down to 0.25V is predicted using ultra-thin 3nm FE-HZO. Next, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultrashort channel FeFETs is utilized to dynamically modulate memory window of storage cells thereby resulting in simple erase-, program-and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and therefore presents a significantly lower power alternative to conventional FeRAM and NOR flash memories

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions

A review of selected topics in physics based modeling for tunnel field-effect transistors

The research field on tunnel-FETs (TFETs) has been rapidly developing in the last ten years, driven by the quest for a new electronic switch operating at a supply voltage well below 1 V and thus delivering substantial improvements in the energy efficiency of integrated circuits. This paper reviews several aspects related to physics based modeling in TFETs, and shows how the description of these transistors implies a remarkable innovation and poses new challenges compared to conventional MOSFETs. A hierarchy of numerical models exist for TFETs covering a wide range of predictive capabilities and computational complexities. We start by reviewing seminal contributions on direct and indirect band-to-band tunneling (BTBT) modeling in semiconductors, from which most TCAD models have been actually derived. Then we move to the features and limitations of TCAD models themselves and to the discussion of what we define non-self-consistent quantum models, where BTBT is computed with rigorous quantum-mechanical models starting from frozen potential profiles and closed-boundary Schr\uf6dinger equation problems. We will then address models that solve the open-boundary Schr\uf6dinger equation problem, based either on the non-equilibrium Green's function NEGF or on the quantum-transmitting-boundary formalism, and show how the computational burden of these models may vary in a wide range depending on the Hamiltonian employed in the calculations. A specific section is devoted to TFETs based on 2D crystals and van der Waals hetero-structures. The main goal of this paper is to provide the reader with an introduction to the most important physics based models for TFETs, and with a possible guidance to the wide and rapidly developing literature in this exciting research field