Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs

A simulation methodology for ultra-scaled InAs quantum well field effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp3d5s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass based ballistic quantum transport model is employed to simulate three terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage magnitude of the QWFETs, (i) the geometry of the gate contact (curved or square) and (ii) the gate metal work function. In addition to pushing the threshold voltage towards an enhancement mode operation, a higher gate metal work function can help suppress the gate leakage and allow for much aggressive insulator scaling

Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs

A simulation methodology for ultra-scaled InAs quantum well field effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp3d5s* tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass based ballistic quantum transport model is employed to simulate three terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I-V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage magnitude of the QWFETs, (i) the geometry of the gate contact (curved or square) and (ii) the gate metal work function. In addition to pushing the threshold voltage towards an enhancement mode operation, a higher gate metal work function can help suppress the gate leakage and allow for much aggressive insulator scaling

Radio Frequency InGaAs MOSFETs

III-V-based Indium gallium arsenide is a promising channel material for high-frequency applications due to its superior electron mobility property. In this thesis, InGaAs/InP heterostructure radio frequency MOSFETs are designed, fabricated, and characterized. Various spacer technologies, from high dielectric spacers to air spacers, are implemented to reduce parasitic capacitances, and fT/fmax are evaluated. Three types of RF MOSFETs with different spacer technologies are fabricated in this work.InP ∧-ridge spacers are integrated on InGaAs Nanowire MOSFET in an attempt to decrease parasitic capacitances; however, due to a high-dielectric constant of the spacers and smaller transistors transconductance, the fT/fmax are limited to 75/100 GHz. InGaAs quantum well MOSFETs with a sacrificial amorphous silicon spacer are fabricated, and they have capacitances of a similar magnitude to other existing high-performing RF InGaAs FETs. An 80 nm InGaAs MOSFET has fT/fmax = 243/147 GHz is demonstrated, and further optimization of the channel and layout would improve the performance. Next, InGaAs MOSFETs with nitride spacer are fabricated in a top-down approach, where the heterostructure is designed to reduce contact resistance and thus improve transconductance. In the first attempt, from the electrical characterization, it is concluded that the ON resistance of these MOSFETs is comparable to state-of-the-art HEMTs. Complete non-quasi-static small-signal modeling is performed on these transistors, and the discrepancy in the magnitude of fmax is discussed. InGaAs/InP 3D-nanosheet/nanowire FETs' high-frequency performance is studied by combining intrinsic analytical and extrinsic numerical models to estimate fT/fmax. 3D vertical stacking results in smaller parasitic capacitances due to electric field perturbance because of screening.An 8-band k⋅p model is implemented to calculate the electronic parameters of strained InxGa1-xAs/InP heterostructure-based quantum wells and nanowires. Bandgap, conduction band energy levels, and their effective masses and non-parabolicity factors are studied for various indium compositions and channel dimensions. These calculated parameters are used to model the long channel quantum well InGaAs MOSFET at cryogenic temperatures, and the importance of band tails limiting the subthreshold slope is discussed

III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2

InGaAs Nanowire and Quantum Well Devices

To fulfill the increasing demand for high-speed electronics used for computation or communication is one everlasting challenge for the semiconductor industry. Emerging fields such as quantum computation also has a need for circuits operating at cryogenic temperatures. The metal-oxide-semiconductor field-effect transistor (MOSFET) is the main component in modern electronics, traditionally fabricated in Si. However, III-V materials generally exhibits higher electron mobility compared to Si. This enables the realization of MOSFETs with higher operational speed or lower power consumption. While a nanowire geometry, where the channel is gated from multiple sides brings an increase in the electrostatic gate control, allowing for further gate length scaling. In this thesis, lateral InGaAs nanowire and quantum well devices have been fabricated and characterized with the purpose of understanding the electron transport and its limitations over a wide temperature range. MOSFETs at cryogenic temperatures, where the phonon occupation is low, are highly sensitive to disorder and defects in the semiconductor/oxide interface. InGaAs RF MOSFETs with different spacer technologies for reducing capacitances have also been fabricated and characterized. Optimizing the spacers for low capacitance and low access resistance is a key design consideration when fabricating devices for high-frequency operation

How do Quantum Effects Influence the Capacitance and Carrier Density of Monolayer MoS2_2 Transistors?

When transistor gate insulators have nanometer-scale equivalent oxide thickness (EOT), the gate capacitance ($C_\textrm{G}$) becomes smaller than the oxide capacitance ($C_\textrm{ox}$) due to the quantum capacitance and charge centroid capacitance of the channel. Here, we study the capacitance of monolayer MoS$_\textrm{2}$ as a prototypical two-dimensional (2D) channel while considering spatial variations in the potential, charge density, and density of states. At 0.5 nm EOT, the monolayer MoS$_\textrm{2}$ capacitance is smaller than its quantum capacitance, limiting the single-gated $C_\textrm{G}$ of an n-type channel to between 63% and 78% of $C_\textrm{ox}$ for gate overdrive voltages between 0.5 and 1 V. Despite these limitations, for dual-gated devices, the on-state $C_\textrm{G}$ of monolayer MoS$_\textrm{2}$ is 50% greater than that of silicon at 0.5 nm EOT and more than three times that of InGaAs at 1 nm EOT, indicating that 2D semiconductors are promising for nanoscale devices at future technology nodes

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) are promising candidatesfor replacing Si-based MOSFETs for future very-large-scale integration (VLSI)logic applications. III-V InGaAs materials have low electron effective mass andhigh electron velocity, allowing higher on-state current at lower VDD and reducingthe switching power consumption. However, III-V InGaAs materials have a nar-rower band gap and higher permittivity, leading to large band-to-band tunneling(BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of thechannel, and large subthreshold leakage due to worse electrostatic integrity. Toutilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have highon-state performance over Si MOSFETs as well as very low leakage current andlow standby power consumption. In this dissertation, we will report InGaAs/InAsultra-thin-body MOSFETs. Three techniques for reducing the leakage currents inInGaAs/InAs MOSFETs are reported as described below.1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-matchto InP by molecular beam epitaxy (MBE), and studied the electron transportin In0.53Ga0.47As/AlAs0.44Sb0.56 heterostructures. The InGaAs channel MOS-FETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage.2) Ultra-thin channels: We investigated the electron transport in InGaAs andInAs ultra-thin quantum wells and ultra-thin body MOSFETs (tch∼2-4 nm).For high performance logic, InAs channels enable higher on-state current, whilefor low power logic, InGaAs channels allow lower BTBT leakage current.3) Source/Drain engineering: We developed raised InGaAs and recessed InPsource/drain spacers. The raised InGaAs source/drain spacers improve electro-statics, reducing subthreshold leakage, and smooth the electric field near drain,reducing BTBT leakage. With further replacement of raised InGaAs spacers byrecessed, doping-graded InP spacers at high field regions, BTBT leakage can bereduced ∼100:1.Using the above-mentioned techniques, record high performance InAs MOS-FETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstratedwith Ion = 500 µA/µm at Ioff = 100 nA/µm and VDS =0.5 V, showing the higheston-state performance among all the III-V MOSFETs and comparable performanceto 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InPsource/drain spacers were also demonstrated with minimum Ioff = 60 pA/µm at30 nm-Lg , and Ion = 150 µA/µm at Ioff = 1 nA/µm and VDS =0.5 V. This re-cessed InP source/drain spacer technique improves device scalability and enablesIII-V MOSFETs for low standby power logic applications. Furthermore, ultra-thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting highyield and high transconductance gm ∼2.0 mS/µm at 20 nm-Lg and VDS =0.5 V.With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown max-imum Ion/Ioff ratio ∼8.3×10 5 , confirming that III-V MOSFETs are scalable tosub-10-nm technology nodes

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Impact of uniaxial strain on P-channel 111-V quantum-well field effect transistors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2012."February 2012." Cataloged from PDF version of thesis.Includes bibliographical references (p. 123-129).Continuous scaling of Si complementary metal-oxide-semiconductor (CMOS) technology requires a boost in carrier injection velocity. With the benefits of strained Si having been exhausted, n-channel I-V quantum-well field effect transistors (QW-FETs) show promising potential as a post-Si CMOS logic technology. To implement complementary circuits, achieving a high-performance p-channel III-V transistor remains one of the grand challenges. The key problem is the low hole mobility in these materials. In this thesis, we investigate a solution to this problem by exploring uniaxial strain as a means to improve hole mobility in III-V quantum-well structures. We have fabricated Hall structures and QW-FETs on several III-V heterostructures. The channels of these heterostructures include n-channel Ino.15Gao.85As, p-channel GaAs, Ino.2 4Gao.76As and Ino.41Gao.59Sb. We applied uniaxial strain to these devices by bending the I-V chips using a mechanical apparatus. Characteristics of these devices were measured while uniaxial strain was externally applied. Significant hole mobility enhancements were observed under uniaxial compressive stress parallel to the transport direction. Our analysis showed that strain-induced valence band deformation is the dominant mechanism. Nevertheless, two other strain effects were found relevant for QWFET operations: Schottky barrier height change and the piezoelectric effect. Threshold voltage (VT) and gate capacitance (CG) of the QW-FETs were found to be changed by these two effects. For the first time, the piezoresistance coefficients for the three pchannel QWs were determined. A significant finding was that the combination of uniaxial strain with epitaxial biaxial strain appears to enhance the hole mobility in a superlinear way. With high piezoresistance coefficients and high hole mobility, InGaSb appears promising for high-performance p-channel QW-FETs for logic applications. We also developed a device architecture for p-channel InGaAs FETs that incorporates uniaxial strain through a self-aligned dielectric stressor. For the first time, we demonstrated substantial enhancements in the transport characteristics of p-channel InGaAs FETs through the combination of compressive uniaxial strain and compressive epitaxially grown biaxial strain. Strain enhances both the intrinsic transconductance as well as the access resistances. The fabricated structure exhibits promising gate-length scalability and compatibility with self-aligned source/drain metal contacts. Our proposed device architecture holds promise to implement high-performance p-channel III-V FETs for future CMOS logic applications.by Ling Xia.Ph.D