Heterostructures for High Performance Devices

Contains table of contents for Part I, table of contents for Section 1, an introduction, reports on eighteen research projects and a list of publications.Charles S. Draper Laboratories Contract DL-H-418483DARPA/NCIPTJoint Services Electronics Program Contract DAAL03-89-C-0001Joint Services Electronics Program Contract DAAL03-92-C-0001IBM Corporation FellowshipNational Science Foundation FellowshipVitesse SemiconductorGTE LaboratoriesCharles S. Draper LaboratoriesElectronics and Telecommunications Research Institute (ETRI) FellowshipNational Science Foundation/Northeastern UniversityTRW SystemsU.S. Army Research OfficeNational Science FoundationAT&T Bell Laboratories FellowshipNational Science Foundation Grant ECS 90-0774

Boundary layer flow and heat transfer over a permeable shrinking sheet with partial slip

The steady, laminar flow of an incompressible viscous fluid over a shrinking permeable sheet is investigated. The governing partial differential equations are transformed into ordinary differential equations using similarity transformation, before being solved numerically by the shooting method. The features of the flow and heat transfer characteristics for different values of the slip parameter and Prandtl number are analyzed and discussed. The results indicate that both the skin friction coefficient and the heat transfer rate at the surface increase as the slip parameter increases

Features of electronic transport in relaxed Si/Si1-X GeX heterostructures with high doping level

The low-temperature electrical and magnetotransport characteristics of partially relaxed Si/Si1-x Gex heterostructures with two-dimensional electron channel (ne≥1012 cm-2) in an elastically strained silicon layer of nanometer thickness have been studied. The detailed calculation of the potential and of the electrons distribution in layers of the structure was carried out to understand the observed phenomena. The dependence of the tunneling transparency of the barrier separating the 2D and 3D transport channels in the structure, was studied as a function of the doping level, the degree of blurring boundaries, layer thickness, degree of relaxation of elastic stresses in the layers of the structure. Tunnel characteristics of the barrier between the layers were manifested by the appearance of a tunneling component in the current-voltage characteristics of real structures. Instabilities, manifested during the magnetotransport measurements using both weak and strong magnetic fields are explained by the transitions of charge carriers from the two-dimensional into three-dimensional state, due to interlayer tunneling transitions of electrons. © 2013 Elsevier B.V. All rights reserved

III-V족 화합물 반도체 터널 전계 효과 트랜지스터 개발

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 최우영.리소그래피 기술의 놀라운 발전은 10 nm 이하의 논리 트랜지스터를 상용화했다. 게이트 길이 스케일링은 모스펫 (MOSFET)의 전력 소비를 줄이기 위한 노력의 큰 부분을 차지한다. 그러나 이러한 접근 방식은 리소그래피의 물리적 한계와 누설 전류 제어와 같은 몇 가지 문제에 직면했다. 모스펫의 근본적인 문제는 현재 전송 메커니즘의 한계로 인해 60 mV/dec 미만의 임계값 기울기 (SS)에 도달할 수 없다는 것이다. Si 터널링 전계효과 트랜지스터 (TFET)의 여러 연구자들이 60 mV/dec 미만의 결과를 보고했지만, Si 동종 접합 터널링 전계효과 트랜지스터는 간접 대역 갭 물질의 터널링 확률이 낮아 전류상으로 불충분하다. P-I 접합부에서의 터널링 확률은 터널링 전계효과 트랜지스터의 동작전류에 영향을 미치기 때문에 작은 직접 밴드갭을 가지고 유효질량이 낮은 III-V 화합물 반도체는 임계값 기울기가 60 mV/dec 미만인 높은 터널링 전류를 달성할 수 있는 가장 유망한 재료이다. 또한 밴드 오프셋이 다른 재료를 선택함으로써, 스태거드 또는 브로큰 갭을 형성함으로써 터널링 전류를 현저하게 증가시킬 수 있다. P-I 접합부의 터널링이 터널 전계효과 트랜지스터 소자의 전류 공급원이기 때문에 많은 연구자들이 분자빔 에피택시 (MBE) 방식으로 성장한 p형 도핑 농도가 높은 III-V 웨이퍼로 제조된 터널 전계효과 트랜지스터의 성능을 보고해왔다. 그러나 높은 도핑 농도와 가파른 도펀트 프로파일을 갖는 p형 InGaAs를 성장하기가 까다롭기 때문에 금속-유기 화학 기상 증착 (MOCVD) 성장 에피택셜 층에서 제조된 InGaAs TFET 소자는 거의 보고되지 않았다. 이에 따라 본 연구는 TFET 소자 제작을 위한 고품질 에피택셜 층을 성장시키기 위한 MOCVD 성장 기술을 선보인다. 종래의 TFET 소자에 대해서는 동종 접합 p-i-n InGaAs 에피택셜층을 성장시키고, p++-Ge/i-InGaAs/n+-InAs 나노선을 성장시켜 TFET 소자 성능 향상 가능성을 확인하였다. MOCVD에 의해 성장한 에피택시 층에서 제조된 TFET 소자의 잠재성을 확인하기 위해 평판과 나노선 에피택셜 층에서 제작된 TFET 소자의 성능이 확인되었다. MOCVD 방법을 이용하여 고품질의 에피택셜 층이 성장되었다. MBE에 비해 가성비, 높은 처리량, 우수한 결정 품질이 MOCVD의 가장 큰 장점이다. 이에 여러 성장 조건을 변화시키면서 InP (001) 기판 위로 InGaAs 필름층의 성장이 연구되었다. 소스 유량, 온도 및 V/III 비율이 성장된 InGaAs 필름층의 품질에 끼치는 영향이 연구되었다. 또한 MOCVD InGaAs 성장 기술에서 n형 및 p형 도펀트의 농도를 높이는 것과 도펀트 프로파일을 가파르게 하는 것이 도전적이므로 탄소 및 텔루륨 도핑을 통해 가파른 도펀트 프로파일을 보이는 고농도의 p형 및 n형 InGaAs층을 성장하였다. 성장된 에피택셜 필름층은 TFET 소자를 제작하여 평가하였다. TFET 소자 제작 전에 우선 TFET 소자의 채널 길이가 전기적 시뮬레이션 결과에 의해 선택되었다. MOCVD를 이용하여 도핑 프로파일이 가파른 고품질의 수직 p-i-n 에피텍셜 구조가 한번에 성장되었다. 에피택셜 성장 후에 TFET 소자는 수직 방향의 습식 식각을 통해 제작되었다. 옴 (Ohmic) 공정과 에어브릿지 공정도 소자 제작을 위해 최적화되었다. P형 도핑 농도에 대한 영향과 MOCVD 성장 중에 생긴 전위에 대한 영향이 TFET 성능을 통하여 확인되었다. 제조된 TFET 소자는 60 mV/dec에 가까운 SS와 괜찮은 온/오프 전류 비율을 보여주었는데, 이는 최초로 보고되는 MBE에서 성장된 웨이퍼에서 만들어진 TFET 소자와 비교할 수 있는 소자이다. 이 결과는 고품질의 MOCVD로 성장한 III-V TFET 소자의 양산 가능성을 보여준다. 이 연구의 다음 부분은 나노선 TFET 제작이다. 전자소자 제작을 위한 III-V 나노선 성장에는 몇 가지 장점이 있다. 다양한 종류의 웨이퍼에 다양한 특성을 가지는 헤테로 구조를 형성할 수 있다는 것이 큰 장점이다. 충분히 작은 직경으로 성장된 나노선은 웨이퍼와 다른 격자 상수를 가지더라도 전위 없는 계면을 가진다. 다양한 유형의 밴드 정렬이 만들어질 수 있으며, 이는 TFET의 터널링 정류를 증가시키는 데에 있어 중요한 요소이다. 또한 직경이 작은 나노선은 칩으로 제작되었을 때 더 나은 소자 밀도, 향상된 게이트 제어성, 성장 시간 단축을 통한 처리량 향상이 가능하다. InGaAs 나노선은 선택적 영역 성장법 (SAG) 성장되었다. 하드마스크 층으로서 InP (111)B 및 Ge (111) 웨이퍼에 SiO2 층이 증착 되었다. 성장 모드가 다르기 때문에 InGaAs 평판 필름층 성장과는 크게 다른 성장 조건을 테스트하였다. 나노선의 선택적 성장은 온도, V/III 비율 및 소스 유량을 최적화하여 확인하였다. 그 결과 InP (111)B와 Ge (111) 웨이퍼에서 InAs와 InGaAs 나노선을 성공적으로 성장시켰다. P형 물질로는 p++도핑된 Ge (111) 웨이퍼를 사용하였다. 인트린식 InGaAs와 InAs 나노선이 그 위에 선택적으로 성장되었다. 마지막으로 실리콘 도펀트를 가진 n형 InAs 나노선이 후속적으로 성장되었다. 성장된 나노선은 수직 나노선 TFET을 제작하여 평가되었다. 높은 단계 커버리지와 양호한 인터페이스 상태 밀도를 위하여 ALD HfO2 및 ALD TiN 공정과정이 최적화되었다. 개발된 ALD 공정을 적용함으로써 수직형 나노선 Ge/InGaAs 헤테로 접합 TFET의 동작이 성공적으로 확인되었다.The remarkable development of lithography technology commercialized the sub-10 nm logic transistors. Gate length scaling is a large portion of the effort to reduce the power consumption of metal-oxide-semiconductor field-effect transistors (MOSFETs). However, this approach faces several problems, such as the physical limitation of lithography and leakage current control. The fundamental problem of MOSFETs is that they cannot reach subthreshold-slope (SS) below 60 mV/dec due to their current transport mechanism. Several researchers of Si tunneling field-effect transistors (TFETs) reported sub-60 mV/dec, but Si homo-junction TFETs show insufficient on-current due to the poor tunneling probability of indirect-band gap materials. As tunneling probability at the p-i junction influences the on-current of TFETs, III-V compound semiconductors, which have a direct small band gap and low effective masses, are the most promising materials to achieve high tunneling current with SS below 60 mV/dec. Also, the tunneling current can be remarkably increased by forming a staggered or broken gap by choosing materials with different band offsets. Since the tunneling at a p-i junction is the current source of TFET devices, many researchers have reported the performance of TFETs fabricated from III-V wafers with high p-type doping concentration grown by the molecular beam epitaxy (MBE) method. However, very few InGaAs TFET devices fabricated on MOCVD-grown epitaxial layers have been reported due to the challenging techniques for achieving p-type InGaAs with high doping concentration and steep dopant profile. Accordingly, this work demonstrates the metal-organic chemical vapor deposition (MOCVD) growth techniques to grow a high-quality epitaxial layer for TFET device fabrication. Homo-junction p-i-n InGaAs epitaxial layers were grown for conventional TFET devices, and hetero-junction p++-Ge/i-InGaAs/n+-InAs nanowires were grown to confirm the possibility of boosting the TFET device performance. The TFET device performance at both epitaxial layers was characterized to confirm the potential of TFET devices fabricated on the epitaxy layers grown by the MOCVD method. The high-quality epitaxial layers were grown using the MOCVD method. Compared to the MBE method, cost-effectiveness, high throughput, and excellent crystal quality are the significant advantages of the MOCVD method. The growth of InGaAs film layers on InP (001) substrate with several growth conditions was studied. The effects of source flow rate, temperature, and V/III ratio on the quality of grown InGaAs film layers were studied. As the high-concentration and steep dopant profile of n-type and p-type dopants are challenging in MOCVD InGaAs growth technique, carbon and tellurium doping techniques were introduced to achieve highly-doped p-type and n-type InGaAs layer with steep dopant profile. The grown epitaxial film layers were evaluated by fabricating the TFET device. Before the TFET device fabrication, the dimensions of the TFET device were selected by electrical simulation results of TFET devices with different structures. For TFET device fabrication, a high-quality vertical p-i-n epitaxial structure with a steep doping profile was successively formed by MOCVD. After epitaxial growth, the TFET devices were fabricated by the vertical top-down wet etching method. The ohmic process and air-bridge process were also optimized for device fabrication. The effect of p-type doping concentration and the dislocations formed during MOCVD growth was confirmed by TFET performance. The fabricated TFET devices showed SS of near-60 mV/dec and sound on/off current ratio, which was by far the first reported device comparable to TFET devices fabricated on the MBE-grown wafers. This result represents the possible mass-production of high-quality MOCVD-grown III-V TFET devices. The next part of this study is nanowire TFET fabrication. The growth of III-V nanowires for electronic device fabrication has several advantages. The significant advantage is that hetero-structures with various characteristics can be formed on various wafers. The nanowires grown by a sufficiently small diameter show a dislocation-free interface even if nanowires have a different lattice constant compared to the wafer. Various types of band-alignment can be formed, and this is a crucial factor in boosting the tunneling current of TFETs. Also, nanowires with a small diameter show better device density in a chip, improved gate controllability, and enhanced throughput by reducing growth time. The InGaAs nanowires were grown by the selective area growth (SAG) method. As a hard-mask layer, a SiO2 layer was deposited on InP (111)B and Ge (111) wafers. Growth conditions far different from InGaAs film layer growth were tested due to the different growth modes. Selective growth of nanowires was identified by optimizing temperature, V/III ratio, and source flow rate. As a result, InAs and InGaAs nanowires were successfully grown on InP (111)B and Ge (111) wafers. For p-type material, the p++-doped Ge (111) wafer was used. The intrinsic InGaAs and InAs nanowires were selectively grown on the patterned substrate. Finally, n-type InAs nanowires with silicon dopant were grown subsequently. The grown nanowires were evaluated by fabricating the vertical nanowire TFETs. ALD HfO2 and ALD TiN processes were optimized for high step coverage and good interface state density. By applying the developed ALD processes, a successful demonstration of vertical nanowire Ge/InGaAs hetero-junction TFET was observed.Contents List of Tables List of Figures Chapter 1. Introduction 1 1.1. Backgrounds 1 1.2. III-V TFETs for Low Power Device 5 1.3. Epitaxy of III-V Materials 12 1.4. Research Aims 17 1.5. References 20 Chapter 2. Epitaxial Growth of InGaAs on InP (001) Substrate 24 2.1. Introduction 24 2.2. Temperature Dependent Properties of Intrinsic-InGaAs on InP (001) Substrate 33 2.3. In-situ Doping Properties of InGaAs on InP (001) Substrate 37 2.4. Conclusion 51 2.5. References 52 Chapter 3. Demonstration of TFET Device Fabricated on InGaAs-on-InP (001) Substrate 56 3.1. Introduction 56 3.2. Simulation of Basic Operations of TFET Device 60 3.3. Process Optimization of TFET Fabrication 68 3.4. Process Flow 74 3.5. Characterization of TFETs Fabricated on MBE-grown and MOCVD-grown Wafers 78 3.6. Conclusion 96 3.7. References 97 Chapter 4. Selective Area Growth of In(Ga)As Nanowires 101 4.1. Introduction 101 4.2. Process Flow of Nanowire Growth 108 4.3. Impact of Different Growth Variables on the Growth of InAs Nanowires 113 4.4. Impact of Different Growth Variables on the Growth of InGaAs Nanowires 127 4.5. Conclusion 144 4.6. References 146 Chapter 5. Demonstration of Vertical Nanowire TFET 149 5.1. Introduction 149 5.2. Optimization of ALD HfO2 High-k Stack 152 5.3. Optimization of ALD TiN Gate Metal 169 5.4. Detailed Demonstration of Vertical Nanowire TFET Fabrication Processes 182 5.5. Characterization of Fabricated Vertical Nanowire TFETs 196 5.6. Conclusion 203 5.7. References 205 Chapter 6. Conclusions and Outlook 209 6.1. Conclusions 209 6.2. Outlook 211 Appendix. 213 A. n+-InAs Nanowire Doping Concentration Evaluation by TLM Method 213 B. n+-InAs Nanowire Doping Concentration Evaluation by C-V Method 219 C. References 205 Abstract in Korean 226 Research Achievements 230박

Heterostructures for High Performance Devices

Contains an introduction, reports on thirteen research projects and a list of publications.Charles S. Draper Laboratory Contract DL-H-418483DARPA/NCIPT Subcontract 542383Joint Services Electronics Program Contract DAAL03-89-C-0001IBM Corporation FellowshipNational Science Foundation FellowshipVitesse SemiconductorAT&T Bell LaboratoriesHertz Foundation FellowshipNational Science FoundationTRWBelgian American Education Foundation (BAEF) FellowshipNational Science Foundation Grant ECS 90-08485Harvard University. Division of Applied PhysicsAT&T Bell Laboratories FellowshipNational Science Foundation Grant ECS 90-0774

Comprehensive Mapping and Benchmarking of Esaki Diode Performance

The tunneling-FET (TFET) has been identified as a prospective MOSFET replacement technology with the potential to extend geometric and electrostatic scaling of digital integrated circuits. However, experimental demonstrations of the TFET have yet to reliably achieve drive currents necessary to power large scale integrated circuits. Consequentially, much effort has gone into optimizing the band-to-band tunneling (BTBT) efficiency of the TFET. In this work, the Esaki tunnel diode (ETD) is used as a short loop element to map and optimize BTBT performance for a large design space. The experimental results and tools developed for this work may be used to (1) map additional and more complicated ETD structures, (2) guide development of improved TFET structures and BTBT devices, (3) design ETDs targeted BTBT characteristics, and (4) calibrate BTBT models. The first objective was to verify the quality of monolithically integrated III-V based ETDs on Si substrates (the industry standard). Five separate GaAs/InGaAs ETDs were fabricated on GaAs-virtual substrates via aspect ratio trapping, along with two companion ETDs grown on Si and GaAs bulk substrates. The quality of the virtual substrates and BTBT were verified with (i) very large peak-valley current ratios (up to 56), (ii) temperature measurements, and (iii) deep sub-micron scaling. The second objective mapped the BTBT characteristics of the In1-xGaxAs ternary system by (1) standardizing the ETD structure, (2) limiting experimental work to unstrained (i) GaAs, (ii) In0.53Ga0.47As, and (iii) InAs homojunctions, and (3) systematically varying doping concentrations. Characteristic BTBT trendlines were determined for each material system, ranging from ultra-low to ultra-high peak current densities (JP) of 11 μA/cm2 to 975 kA/cm2 for GaAs and In0.53Ga0.47As, respectively. Furthermore, the BTBT mapping results establishes that BTBT current densities can only be improved by ~2-3 times the current record, by increasing doping concentration and In content up to ~75%. The E. O. Kane BTBT model has been shown to accurately predict the tunneling characteristics for the entire design space. Furthermore, it was used to help guide the development of a new universal BTBT model, which is a closed form exponential using 2 fitting parameters, material constants, and doping concentrations. With it, JP can quickly be predicted over the entire design space of this work

Vertical III-V Nanowire Transistors for Low-Power Electronics

Power dissipation has been the major challenge in the downscaling of transistor technology. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have struggled to keep a low power consumption while still maintaining a high performance due to the low carrier mobilities of Si but also due to their inherent minimum inverse subthreshold slope (S ≥ 60 mV/dec) which is limited by thermionic emission. This thesis work studied the capabilities and limitations of III-V based vertical nanowire n-type Tunneling Field-Effect Transistor (TFET) and p-type MOSFET (PMOS). InAs/InGaAsSb/GaSb heterojunction was employed in the whole study. The main focus was to understand the influence of the device fabrication processes and the structural factors of the nanowires such as band alignment, composition and doping on the electrical performance of the TFET. Optimizations of the device processes including spacer technology improvement, Equivalent Oxide Thickness (EOT) downscaling, and gate underlap/overlap were explored utilizing structural characterizations. Systematic fine tuning of the band alignment of the tunnel junction resultedin achieving the best performing sub-40 mV/dec TFETs with S = 32 mV/decand ION = 4μA/μm for IOFF = 1 nA/μm at VDS = 0.3 V. The suitability of employing TFET for electronic applications at cryogenic temperatures has been explored utilizing experimental device data. The impact of the choice of heterostructure and dopant incorporation were investigated to identify the optimum operating temperature and voltage in different temperature regimes. A novel gate last process self-aligning the gate and drain contacts to the intrinsic and doped segments, respectively was developed for vertical InGaAsSb-GaAsSb core-shell nanowire transistors leading to the first sub-100 mV/dec PMOS with S = 75 mV/dec, significant ION/ IOFF = 104 and IMIN < 1 nA/μm at VDS = -0.5 V