Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

Synthesis of time-to-amplitude converter by mean coevolution with adaptive parameters

Copyright © 2011 the authors and Scientific Research Publishing Inc. This work is licensed under a Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/)The challenging task to synthesize automatically a time-to-amplitude converter, which unites by its functionality several digital circuits, has been successfully solved with the help of a novel methodology. The proposed approach is based on a paradigm according to which the substructures are regarded as additional mutation types and when ranged with other mutations form a new adaptive individual-level mutation technique. This mutation approach led to the discovery of an original coevolution strategy that is characterized by very low selection rates. Parallel island-model evolution has been running in a hybrid competitive-cooperative interaction throughout two incremental stages. The adaptive population size is applied for synchronization of the parallel evolutions

Automatic design of analogue circuits

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits

Small Magnetic Sensors for Space Applications

Small magnetic sensors are widely used integrated in vehicles, mobile phones, medical devices, etc for navigation, speed, position and angular sensing. These magnetic sensors are potential candidates for space sector applications in which mass, volume and power savings are important issues. This work covers the magnetic technologies available in the marketplace and the steps towards their implementation in space applications, the actual trend of miniaturization the front-end technologies, and the convergence of the mature and miniaturized magnetic sensor to the space sector through the small satellite concept

25 years of network access technologies: from voice to internet; the changing face of telecommunications

This work contributes to knowledge in the field of semiconductor system architectures, circuit design and implementation, and communications protocols. The work starts by describing the challenges of interfacing legacy analogue subscriber loops to an electronic circuit contained within the Central Office (Telephone Exchange) building. It then moves on to describe the globalisation of the telecom network, the demand for software programmable devices to enable system customisation cost effectively, and the creation of circuit and system blocks to realise this. The work culminates in the application challenges of developing a wireless RF front end, including antenna, for an Ultra Wideband communications systems applications. This thesis illustrates how higher levels of integration over the period of 1981 to 2010 have influenced the realisation of complex system level products, particularly analogue signal processing capabilities for communications applications. There have been many publications illustrating the impact of technology advancement from an economic or technology perspective. The thesis shows how technology advancement has impacted the physical realisation of semiconductor products over the period, at system, circuit, and physical implementation levels

Design and analysis of a 2.5-GHz optical receiver analog front-end using geiger mode photodiode in a 0.13 μm CMOS process

The optical receiver analog front-end using geiger mode photodiode have several design challenges, especially in high-speed application. The parasitic capacitance (CPD) of the geiger mode photodiode (PD) is large, can be several pico farads which significantly limits the bandwidth (BW) of the geiger mode photodiode. In addition, a very weak current signal which is generated by the geiger mode photodiode limits the number of photon count by the receiver circuit. To address this problem, the amplification stage followed the geiger mode photodiode must be designed to amplify the detected signal using a low voltage CMOS process device. Hence, low input impedance amplifier topologies such as common gate (CG) transimpedance amplifier (TIA) is usually employed. The applications of optical receiver are in high-speed optical communication system. Therefore, it is essential for the analog front-end (AFE) receiver (RX) which consists the PD and TIA to have a large bandwidth, usually in the range of several GHz. This project aims to design a 2.5 GHz optical AFE RX using PD in a 0.13 μm CMOS process. To comprehend the limitation of previous TIA topologies which have designed by the other researcher, these topologies are designed and simulated in lower supply voltage at 1.2 V and 0.13 μm CMOS process to assist the characterization of proposed TIA circuit for this project. Pre-layout simulation is performed and the circuit performance is analysed to define the topology that give the best performance to be used. Post layout simulation is performed on the chosen design. CG TIA is justified to be used in this project as the literature shows that it can achieve BW larger than 2.5 GHz compared to common source (CS) TIA. As a result, two TIAs which are the CG with common source active feedback (CSFB) and regulated cascode (RGC) are compared. With ideal resistor and ideal current source, the RGC outperformed CSFB in term of BW and gain. Hence, this project employed RGC topology to achieve the objective. The ideal circuit components are replaced with CMOS circuit to improve area and make the entire circuit fully on-chip. The BW achieved by the designed RGC TIA is 2.47 GHz with a TI gain of 53.8 dBΩ under large CPD of 2 pF. It is proven by this work that the RGC TIA is capable operating in the GHz frequency range with large CPD even the process shrink to 0.13 μm and the supply reduced to 1.2 V

Kazakhstan's Diversification from the Natural Resources Sector: Strategic and Economic Opportunities

This book explores opportunities for diversifying modern Kazakhstan's economy, which is still heavily dependent on its natural resources, as well as looking at economic opportunities for the whole Central Asian region arising from the Chinese government's Belt and Road Initiative (BRI). The book is comprised of four parts. Part 1 explores the first main theme of the book: development of the economy based on the resource sector with the example of Kazakhstan. Part 2 examines opportunities for diversification arising from BRI: a rise of transport and communication industries alongside the new Belt and Road economic route. Part 3 explores the view from China on the perspectives of regional development, not least the economic reasons for the launch of this programme, investments and planned effects. Part 4 discusses other internal sources for diversification of the economy in Kazakhstan based on development of local industry in the oil and gas sector, small- and medium-sized enterprises and tertiary sector of the economy. This book will be of value for students, academics, policy-makers, and practitioners focused on economic development and business in the Central Asian region, as well as those who are working on the design of instruments for economic development in their own countries