13 research outputs found

    Improved fault tolerance of Turbo decoding based on optimized index assignments

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    Reconfigurable architectures for beyond 3G wireless communication systems

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    Software implementation and performance of UMTS turbo code

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    In the recent years, there has been a proliferation of wireless standards in television, radio and mobile communications. As a result, compatibility issues have emerged in wireless networks. The size, cost and competitiveness set limitations on implementing systems compatible with multiple standards. This has motivated the concept of software defined radio which can support different standards by reloading the software and implementing computationally intensive parts on hardware, e.g., iterative codes. In a typical communication system, all the processing is done in the digital domain. The information is represented as a sequence of bits which is modulated on an analog waveform and transmitted over the communication channel. Due to channel induced impairments, the received signal may not be a true replica of the transmitted signal. Thus, some error control is required which is achieved by the use of channel coding schemes that protect the signal from the effects of channel and help to reduce the bit error rate (BER) and improve reliability of information transmission. Shannon gave the theoretical upper bound on the channel capacity for a given bandwidth, data rate and signal-to-noise ratio in 1940s but practical codes were unable to operate even close to the theoretical bound. Turbo codes were introduced in 1993 where a scheme was described that was able to operate very close to the Shannon limit. Turbo codes are widely used in latest wireless standards e.g. UMTS and LTE. A basic turbo encoder consists of two or more component encoders concatenated in parallel and separated by an interleaver. The turbo decoder uses soft decision to decode the bits and the decoding is done in an iterative fashion to increase reliability of the decision. In this thesis, the turbo code for the UMTS standard is implemented in MATLAB. Four versions of the Maximum Aposteriori Probability (MAP) algorithm are used in the implementation. The simulation results show that the performance of the turbo code improves by increasing the number of iterations. Also, better performance can be achieved by increasing the frame size or the interleaver size and increasing the signal power. Overall, the designing of turbo codes is a trade-off between energy efficiency, bandwidth efficiency, complexity and error performance

    VLSI Architectures for WIMAX Channel Decoders

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    This chapter describes the main architectures proposed in the literature to implement the channel decoders required by the WiMax standard, namely convolutional codes, turbo codes (both block and convolutional) and LDPC. Then it shows a complete design of a convolutional turbo code encoder/decoder system for WiMax.Comment: To appear in the book "WIMAX, New Developments", M. Upena, D. Dalal, Y. Kosta (Ed.), ISBN978-953-7619-53-

    A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip

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    Domain specific high performance reconfigurable architecture for a communication platform

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    Soft-demodulation of QPSK and 16-QAM for turbo coded WCDMA mobile communication systems

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    EThOS - Electronic Theses Online ServiceGBUnited Kingdo

    Energy-efficient design and implementation of turbo codes for wireless sensor network

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    The objective of this thesis is to apply near Shannon limit Error-Correcting Codes (ECCs), particularly the turbo-like codes, to energy-constrained wireless devices, for the purpose of extending their lifetime. Conventionally, sophisticated ECCs are applied to applications, such as mobile telephone networks or satellite television networks, to facilitate long range and high throughput wireless communication. For low power applications, such as Wireless Sensor Networks (WSNs), these ECCs were considered due to their high decoder complexities. In particular, the energy efficiency of the sensor nodes in WSNs is one of the most important factors in their design. The processing energy consumption required by high complexity ECCs decoders is a significant drawback, which impacts upon the overall energy consumption of the system. However, as Integrated Circuit (IC) processing technology is scaled down, the processing energy consumed by hardware resources reduces exponentially. As a result, near Shannon limit ECCs have recently begun to be considered for use in WSNs to reduce the transmission energy consumption [1,2]. However, to ensure that the transmission energy consumption reduction granted by the employed ECC makes a positive improvement on the overall energy efficiency of the system, the processing energy consumption must still be carefully considered.The main subject of this thesis is to optimise the design of turbo codes at both an algorithmic and a hardware implementation level for WSN scenarios. The communication requirements of the target WSN applications, such as communication distance, channel throughput, network scale, transmission frequency, network topology, etc, are investigated. Those requirements are important factors for designing a channel coding system. Especially when energy resources are limited, the trade-off between the requirements placed on different parameters must be carefully considered, in order to minimise the overall energy consumption. Moreover, based on this investigation, the advantages of employing near Shannon limit ECCs in WSNs are discussed. Low complexity and energy-efficient hardware implementations of the ECC decoders are essential for the target applications

    Energy efficient design of an adaptive switching algorithm for the iterative-MIMO receiver

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    An efficient design dedicated for iterative-multiple-input multiple-output (MIMO) receiver systems is now imperative in our world since data demands are increasing tremendously in wireless networks. This puts a massive burden on the signal processing power especially in small receiver systems where power sources are often shared or limited. This thesis proposes an attractive solution to both the wireless signal processing and the architectural implementation design sides of the problem. A novel algorithm, dubbed the Adaptive Switching Algorithm, is proven to not only save more than a third of the energy consumption in the algorithmic design, but is also able to achieve an energy reduction of more than 50% in terms of processing power when the design is mapped onto state-of-the-art programmable hardware. Simulations are based in MatlabTM using the Monte Carlo approach, where multiple additive white Gaussian noise (AWGN) and Rayleigh fading channels for both fast and slow fading environments were investigated. The software selects the appropriate detection algorithm depending on the current channel conditions. The design for the hardware is based on the latest field programmable gate arrays (FPGA) hardware from Xilinx R , specifically the Virtex-5 and Virtex-7 chipsets. They were chosen during the experimental phase to verify the results in order to examine trends for energy consumption in the proposed algorithm design. Savings come from dynamic allocation of the hardware resources by implementing power minimization techniques depending on the processing requirements of the system. Having demonstrated the feasibility of the algorithm in controlled environments, realistic channel conditions were simulated using spatially correlated MIMO channels to test the algorithm’s readiness for real-world deployment. The proposed algorithm is placed in both the MIMO detector and the iterative-decoder blocks of the receiver. When the final full receiver design setup is implemented, it shows that the key to energy saving lies in the fact that both software and hardware components of the Adaptive Switching Algorithm adopt adaptivity in the respective designs. The detector saves energy by selecting suitable detection schemes while the decoder provides adaptivity by limiting the number of decoding iterations, both of which are updated in real-time. The overall receiver can achieve more than 70% energy savings in comparison to state-of-the-art iterative-MIMO receivers and thus it can be concluded that this level of ‘intelligence’ is an important direction towards a more efficient iterative-MIMO receiver designs in the future

    Coded cooperative diversity with low complexity encoding and decoding algorithms.

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    One of the main concerns in designing the wireless communication systems is to provide sufficiently large data rates while considering the different aspects of the implementation complexity that is often constrained by limited battery power and signal processing capability of the devices. Thus, in this thesis, a low complexity encoding and decoding algorithms are investigated for systems with the transmission diversity, particularly the receiver diversity and the cooperative diversity. Design guidelines for such systems are provided to provide a good trade-off between the implementation complexity and the performance. The order statistics based list decoding techniques for linear binary block codes of small to medium block length are investigated to reduce the complexity of coded systems. The original order statistics decoding (OSD) is generalized by assuming segmentation of the most reliable independent positions of the received bits. The segmentation is shown to overcome several drawbacks of the original order statistics decoding. The complexity of the OSD is further reduced by assuming a partial ordering of the received bits in order to avoid the highly complex Gauss elimination. The bit error rate performance and the decoding complexity trade-off of the proposed decoding algorithms are studied by computer simulations. Numerical examples show that, in some cases, the proposed decoding schemes are superior to the original order statistics decoding in terms of both the bit error rate performance as well as the decoding complexity. The complexity of the order statistics based list decoding algorithms for linear block codes and binary block turbo codes (BTC) is further reduced by employing highly reliable cyclic redundancy check (CRC) bits. The results show that sending CRC bits for many segments is the most effective tecnhique in reducing the complexity. The coded cooperative diversity is compared with the conventional receiver coded diversity in terms of the pairwise error probability and the overall bit error rate (BER). The expressions for the pairwise error probabilities are obtained analytically and verified by computer simulations. The performance of the cooperative diversity is found to be strongly relay location dependent. Using the analytical as well as extensive numerical results, the geographical areas of the relay locations are obtained for small to medium signal-to-noise ratio values, such that the cooperative coded diversity outperforms the receiver coded diversity. However, for sufficiently large signal-to-noise ratio (SNR) values, or if the path-loss attenuations are not considered, then the receiver coded diversity always outperforms the cooperative coded diversity. The obtained results have important implications on the deployment of the next generation cellular systems supporting the cooperative as well as the receiver diversity
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