9,105 research outputs found
On Compact Routing for the Internet
While there exist compact routing schemes designed for grids, trees, and
Internet-like topologies that offer routing tables of sizes that scale
logarithmically with the network size, we demonstrate in this paper that in
view of recent results in compact routing research, such logarithmic scaling on
Internet-like topologies is fundamentally impossible in the presence of
topology dynamics or topology-independent (flat) addressing. We use analytic
arguments to show that the number of routing control messages per topology
change cannot scale better than linearly on Internet-like topologies. We also
employ simulations to confirm that logarithmic routing table size scaling gets
broken by topology-independent addressing, a cornerstone of popular
locator-identifier split proposals aiming at improving routing scaling in the
presence of network topology dynamics or host mobility. These pessimistic
findings lead us to the conclusion that a fundamental re-examination of
assumptions behind routing models and abstractions is needed in order to find a
routing architecture that would be able to scale ``indefinitely.''Comment: This is a significantly revised, journal version of cs/050802
Scalable Routing Easy as PIE: a Practical Isometric Embedding Protocol (Technical Report)
We present PIE, a scalable routing scheme that achieves 100% packet delivery
and low path stretch. It is easy to implement in a distributed fashion and
works well when costs are associated to links. Scalability is achieved by using
virtual coordinates in a space of concise dimensionality, which enables greedy
routing based only on local knowledge. PIE is a general routing scheme, meaning
that it works on any graph. We focus however on the Internet, where routing
scalability is an urgent concern. We show analytically and by using simulation
that the scheme scales extremely well on Internet-like graphs. In addition, its
geometric nature allows it to react efficiently to topological changes or
failures by finding new paths in the network at no cost, yielding better
delivery ratios than standard algorithms. The proposed routing scheme needs an
amount of memory polylogarithmic in the size of the network and requires only
local communication between the nodes. Although each node constructs its
coordinates and routes packets locally, the path stretch remains extremely low,
even lower than for centralized or less scalable state-of-the-art algorithms:
PIE always finds short paths and often enough finds the shortest paths.Comment: This work has been previously published in IEEE ICNP'11. The present
document contains an additional optional mechanism, presented in Section
III-D, to further improve performance by using route asymmetry. It also
contains new simulation result
Compact Routing on Internet-Like Graphs
The Thorup-Zwick (TZ) routing scheme is the first generic stretch-3 routing
scheme delivering a nearly optimal local memory upper bound. Using both direct
analysis and simulation, we calculate the stretch distribution of this routing
scheme on random graphs with power-law node degree distributions, . We find that the average stretch is very low and virtually
independent of . In particular, for the Internet interdomain graph,
, the average stretch is around 1.1, with up to 70% of paths
being shortest. As the network grows, the average stretch slowly decreases. The
routing table is very small, too. It is well below its upper bounds, and its
size is around 50 records for -node networks. Furthermore, we find that
both the average shortest path length (i.e. distance) and width of
the distance distribution observed in the real Internet inter-AS graph
have values that are very close to the minimums of the average stretch in the
- and -directions. This leads us to the discovery of a unique
critical quasi-stationary point of the average TZ stretch as a function of
and . The Internet distance distribution is located in a
close neighborhood of this point. This observation suggests the analytical
structure of the average stretch function may be an indirect indicator of some
hidden optimization criteria influencing the Internet's interdomain topology
evolution.Comment: 29 pages, 16 figure
Near-optimal adjacency labeling scheme for power-law graphs
An adjacency labeling scheme is a method that assigns labels to the vertices
of a graph such that adjacency between vertices can be inferred directly from
the assigned label, without using a centralized data structure. We devise
adjacency labeling schemes for the family of power-law graphs. This family that
has been used to model many types of networks, e.g. the Internet AS-level
graph. Furthermore, we prove an almost matching lower bound for this family. We
also provide an asymptotically near- optimal labeling scheme for sparse graphs.
Finally, we validate the efficiency of our labeling scheme by an experimental
evaluation using both synthetic data and real-world networks of up to hundreds
of thousands of vertices
Pruning based Distance Sketches with Provable Guarantees on Random Graphs
Measuring the distances between vertices on graphs is one of the most
fundamental components in network analysis. Since finding shortest paths
requires traversing the graph, it is challenging to obtain distance information
on large graphs very quickly. In this work, we present a preprocessing
algorithm that is able to create landmark based distance sketches efficiently,
with strong theoretical guarantees. When evaluated on a diverse set of social
and information networks, our algorithm significantly improves over existing
approaches by reducing the number of landmarks stored, preprocessing time, or
stretch of the estimated distances.
On Erd\"{o}s-R\'{e}nyi graphs and random power law graphs with degree
distribution exponent , our algorithm outputs an exact distance
data structure with space between and
depending on the value of , where is the number of vertices. We
complement the algorithm with tight lower bounds for Erdos-Renyi graphs and the
case when is close to two.Comment: Full version for the conference paper to appear in The Web
Conference'1
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
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