7 research outputs found
Hardware Parallelization of Cores Accessing Memory with Irregular Access Patterns
Full text linkThis project studies FPGA-based heterogeneous computing architectures with the objective of
discovering their ability to optimize the performances of algorithms characterized by irregular
memory access patterns. The example used to achieve this is a graph algorithm known as Triad
Census Algorithm, whose implementation has been developed and tested.
First of all, the triad census algorithm is presented, explaining the possible variants and
reviewing the existing implementations upon different architectures. The analysis focuses on
the parallelization techniques which have allowed to boost performance, thus reducing execution
time. Besides, the study tackles the OpenCL programming model, the standard used to develop
the final application. Special attention is paid to the language details that have motivated some
of the most important design decisions.
The dissertation continues with the description of the project implementation, including
the application objectives, the system design, and the different variants developed to enhance
algorithm performance.
Finally, some of the experimental results are presented and discussed. All implemented
versions are evaluated and compared to decide which is the best in terms of scalability and
execution time
