VHDL implementation and synthesis of adaptive thresholding

As the world of mobile multimedia computing continues to grow, so does the need for small, high performance, low power microchips. The implementation of the software algorithms used in these systems therefore has become an increasingly important issue in more recent applications. In order to realize the goals of our technological society and keep up with the speed at which computing technology is growing, the hardware implementation of these algorithms must be examined. This thesis describes the implementation and system simulation of four image binarization algorithms. The first algorithm is a simple global thresholding algorithm, while the remaining three adapt to the luminescent properties of the image. A high-level design philosophy was utilized throughout the course of the research. Each algorithm was first modeled in MATLAB, implemented and simulated in VHDL, and then synthesized to an FPGA where their operation was tested using a custom PC interface. High-level programming methods were used in both the modeling and VHDL implementations of the algorithms. The algorithms were synthesized to an Altera 20K200E FPGA on the Excalibur NIOS development board. Of the four algorithms, the local thresholding algorithm would not synthesize due to the high-level VHDL loop commands which were utilized in the implementation. The remaining three, global thresholding, running average thresholding, and quick adaptive thresholding were synthesized and written to the target device with 7.12%, 89.76% and 58.52% utilization of the devices on the FPGA respectively. The global thresholding algorithm achieved a clock frequency of 62.1 MHz, running thresholding achieved 17.6 MHz, and quick thresholding obtained a frequency of 21.4 MHz

Efficient Hardware Design Of Iterative Stencil Loops

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task. In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, sub-portions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually-optimized solutions, and orders of magnitude higher than those generated by commercial HLS tools

Power-Aware Design Methodologies for FPGA-Based Implementation of Video Processing Systems

The increasing capacity and capabilities of FPGA devices in recent years provide an attractive option for performance-hungry applications in the image and video processing domain. FPGA devices are often used as implementation platforms for image and video processing algorithms for real-time applications due to their programmable structure that can exploit inherent spatial and temporal parallelism. While performance and area remain as two main design criteria, power consumption has become an important design goal especially for mobile devices. Reduction in power consumption can be achieved by reducing the supply voltage, capacitances, clock frequency and switching activities in a circuit. Switching activities can be reduced by architectural optimization of the processing cores such as adders, multipliers, multiply and accumulators (MACS), etc. This dissertation research focuses on reducing the switching activities in digital circuits by considering data dependencies in bit level, word level and block level neighborhoods in a video frame. The bit level data neighborhood dependency consideration for power reduction is illustrated in the design of pipelined array, Booth and log-based multipliers. For an array multiplier, operands of the multipliers are partitioned into higher and lower parts so that the probability of the higher order parts being zero or one increases. The gating technique for the pipelined approach deactivates part(s) of the multiplier when the above special values are detected. For the Booth multiplier, the partitioning and gating technique is integrated into the Booth recoding scheme. In addition, a delay correction strategy is developed for the Booth multiplier to reduce the switching activities of the sign extension part in the partial products. A novel architecture design for the computation of log and inverse-log functions for the reduction of power consumption in arithmetic circuits is also presented. This also utilizes the proposed partitioning and gating technique for further dynamic power reduction by reducing the switching activities. The word level and block level data dependencies for reducing the dynamic power consumption are illustrated by presenting the design of a 2-D convolution architecture. Here the similarities of the neighboring pixels in window-based operations of image and video processing algorithms are considered for reduced switching activities. A partitioning and detection mechanism is developed to deactivate the parallel architecture for window-based operations if higher order parts of the pixel values are the same. A neighborhood dependent approach (NDA) is incorporated with different window buffering schemes. Consideration of the symmetry property in filter kernels is also applied with the NDA method for further reduction of switching activities. The proposed design methodologies are implemented and evaluated in a FPGA environment. It is observed that the dynamic power consumption in FPGA-based circuit implementations is significantly reduced in bit level, data level and block level architectures when compared to state-of-the-art design techniques. A specific application for the design of a real-time video processing system incorporating the proposed design methodologies for low power consumption is also presented. An image enhancement application is considered and the proposed partitioning and gating, and NDA methods are utilized in the design of the enhancement system. Experimental results show that the proposed multi-level power aware methodology achieves considerable power reduction. Research work is progressing In utilizing the data dependencies in subsequent frames in a video stream for the reduction of circuit switching activities and thereby the dynamic power consumption

Traitement des images bidimensionnelles à l'aide des FPGAs

Les images sont de plus en plus utilisées dans de nombreuses disciplines (télédétection, médecine, etc.) car elles fournissent des informations précieuses sur les scènes ou les objets filmés. En médecine, depuis quelques années, les images sont devenues des éléments indispensables à l'établissement d'un bon diagnostic. Quelquefois, il apparaît qu'une image brute ne fournit pas tous les détails nécessaires à une bonne analyse, elle doit être retouchée de diverses manières : c'est le traitement des images. De nombreux algorithmes ont été mis au point pour effectuer des traitements d'images; certains présentent une complexité algorithmique élevée, ce qui fait que le temps de calcul pour traiter une image peut vite devenir exorbitant (cas des filtres, redimensionnement) dans les architectures monoprocesseurs. Afin d'accélérer le travail des radiologues dans l'analyse des images, nous avons recours au calcul parallèle. Les FPGAs (Field-Programmable Gate Arrays) sont des circuits électroniques parallèles qui permettent aujourd'hui de développer des applications de plus en plus performantes en vitesse d'exécution et gourmandes en ressources matérielles. Dans le cadre de notre travail de recherche, nous mettons en ?uvre, sur FPGA, quelques algorithmes de traitement d'images et nous étudions la faisabilité des traitements en temps réel (idéalement, 20 traitements par seconde ou 1 image toutes les 50 ms). Le langage de programmation que nous utilisons dans notre étude est psC. Nos travaux permettent de tester la puissance de ce langage dans le déploiement d'applications sur FPGA et ils contribuent à son amélioration

Pervasive handheld computing systems

The technological role of handheld devices is fundamentally changing. Portable computers were traditionally application specific. They were designed and optimised to deliver a specific task. However, it is now commonly acknowledged that future handheld devices need to be multi-functional and need to be capable of executing a range of high-performance applications. This thesis has coined the term pervasive handheld computing systems to refer to this type of mobile device. Portable computers are faced with a number of constraints in trying to meet these objectives. They are physically constrained by their size, their computational power, their memory resources, their power usage, and their networking ability. These constraints challenge pervasive handheld computing systems in achieving their multi-functional and high-performance requirements. This thesis proposes a two-pronged methodology to enable pervasive handheld computing systems meet their future objectives. The methodology is a fusion of two independent and yet complementary concepts. The first step utilises reconfigurable technology to enhance the physical hardware resources within the environment of a handheld device. This approach recognises that reconfigurable computing has the potential to dynamically increase the system functionality and versatility of a handheld device without major loss in performance. The second step of the methodology incorporates agent-based middleware protocols to support handheld devices to effectively manage and utilise these reconfigurable hardware resources within their environment. The thesis asserts the combined characteristics of reconfigurable computing and agent technology can meet the objectives of pervasive handheld computing systems

Implementing Image Applications on FPGAs

The Cameron project has developed a language and compiler for mapping image-based applications to field programmable gate arrays (FPGAs). This paper tests this technology on several applications and finds that FPGAs are between 8 and 800 times faster than comparable Pentiums for image based tasks