34 research outputs found
Data Acquisition Applications
Data acquisition systems have numerous applications. This book has a total of 13 chapters and is divided into three sections: Industrial applications, Medical applications and Scientific experiments. The chapters are written by experts from around the world, while the targeted audience for this book includes professionals who are designers or researchers in the field of data acquisition systems. Faculty members and graduate students could also benefit from the book
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)
ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability
BASEBAND RADIO MODEM DESIGN USING GRAPHICS PROCESSING UNITS
A modern radio or wireless communications transceiver is programmed via
software and firmware to change its functionalities at the baseband. However, the
actual implementation of the radio circuits relies on dedicated hardware, and the
design and implementation of such devices are time consuming and challenging. Due
to the need for real-time operation, dedicated hardware is preferred in order to meet
stringent requirements on throughput and latency. With increasing need for higher
throughput and shorter latency, while supporting increasing bandwidth across a
fragmented spectrum, dedicated subsystems are developed in order to service individual
frequency bands and specifications. Such a dedicated-hardware-intensive
approach leads to high resource costs, including costs due to multiple instantiations
of mixers, filters, and samplers. Such increases in hardware requirements in turn
increases device size, power consumption, weight, and financial cost.
If it can meet the required real-time constraints, a more flexible and reconfigurable
design approach, such as a software-based solution, is often more desirable
over a dedicated hardware solution. However, significant challenges must be
overcome in order to meet constraints on throughput and latency while servicing
different frequency bands and bandwidths. Graphics processing unit (GPU) technology
provides a promising class of platforms for addressing these challenges. GPUs,
which were originally designed for rendering images and video sequences, have been
adapted as general purpose high-throughput computation engines for a wide variety
of application areas beyond their original target domains. Linear algebra and signal
processing acceleration are examples of such application areas.
In this thesis, we apply GPUs as software-based, baseband radios and demonstrate
novel, software-based implementations of key subsystems in modern wireless
transceivers. In our work, we develop novel implementation techniques that allow
communication system designers to use GPUs as accelerators for baseband processing
functions, including real-time filtering and signal transformations. More
specifically, we apply GPUs to accelerate several computationally-intensive, frontend
radio subsystems, including filtering, signal mixing, sample rate conversion,
and synchronization. These are critical subsystems that must operate in real-time
to reliably receive waveforms.
The contributions of this thesis can be broadly organized into 3 major areas:
(1) channelization, (2) arbitrary resampling, and (3) synchronization.
1. Channelization: a wideband signal is shared between different users and
channels, and a channelizer is used to separate the components of the shared signal
in the different channels. A channelizer is often used as a pre-processing step in
selecting a specific channel-of-interest. A typical channelization process involves signal
conversion, resampling, and filtering to reject adjacent channels. We investigate
GPU acceleration for a particularly efficient form of channelizer called a polyphase
filterbank channelizer, and demonstrate a real-time implementation of our novel
channelizer design.
2. Arbitrary resampling: following a channelization process, a signal is often
resampled to at least twice the data rate in order to further condition the signal.
Since different communication standards require different resampling ratios, it is
desirable for a resampling subsystem to support a variety of different ratios. We
investigate optimized, GPU-based methods for resampling using polyphase filter
structures that are mapped efficiently into GPU hardware. We investigate these
GPU implementation techniques in the context of interpolation (integer-factor increases
in sampling rate), decimation (integer-factor decreases in sampling rate),
and rational resampling. Finally, we demonstrate an efficient implementation of arbitrary
resampling using GPUs. This implementation exploits specialized hardware
units within the GPU to enable efficient and accurate resampling processes involving
arbitrary changes in sample rate.
3. Synchronization: incoming signals in a wireless communications transceiver
must be synchronized in order to recover the transmitted data properly from complex
channel effects such as thermal noise, fading, and multipath propagation. We investigate
timing recovery in GPUs to accelerate the most computationally intensive
part of the synchronization process, and correctly align the incoming data symbols
in the receiver. Furthermore, we implement fully-parallel timing error detection to
accelerate maximum likelihood estimation
dsPIC-based signal processing techniques and an IT-enabled distributed system for intelligent process monitoring and management
dsPIC Technology employs a powerful 16-bit architecture into single-chip devices that seamlessly integrate the diverse attributes of a microcontroller with the computation and throughput capabilities of a digital signal processor in a single core. The key element of this dissertation is to explore how dsPIC has influenced the applicability of research in e-Monitoring systems. At the same time dsPIC has offered the opportunity to develop methodologies which were previously not even considered. The dsPIC devices are used, in this research, for front end data acquisition, signal processing and communication tools within a proposed monitoring architecture. In this work, novel digital signal processing (DSP) techniques are developed for the monitoring of an example application, namely the challenging one of tool breakage in milling operations. The monitoring regime is implemented on the dsPIC and its capabilities for real-time frequency analysis using overlap FFT and Multiband IIR Filters with dynamic coefficient selection techniques is explored. The developed systems are tested for various cutting conditions using existing machine tool signals and tool breakage is detected reliably in real-time. In attempting to enhance the accuracy of tool monitoring it is evident that the depth of cut (DOC) is an important parameter and achieving its on-line monitoring provides valuable information for condition monitoring. A systematic approach is adopted for the analysis and selection of ultrasonic sensors for distance measurement. A DOC monitoring system is developed using the dsPIC as the data acquisition and processing core. To achieve reliable results, various DSP algorithms are developed, implemented and verified for their effectiveness. The system integration stage combines the above elements for robust and reliable decision making and provides communication of the generated information to support management function using the internet and GSM connectivity. This integration enables an enhanced process management system which is capable of identifying all significant events, for offline analysis and subsequent diagnosis in addition to the real time diagnostic mode
Design for prognostics and security in field programmable gate arrays (FPGAs).
There is an evolutionary progression of Field Programmable Gate Arrays (FPGAs)
toward more complex and high power density architectures such as Systems-on-
Chip (SoC) and Adaptive Compute Acceleration Platforms (ACAP). Primarily, this is
attributable to the continual transistor miniaturisation and more innovative and
efficient IC manufacturing processes. Concurrently, degradation mechanism of Bias
Temperature Instability (BTI) has become more pronounced with respect to its
ageing impact. It could weaken the reliability of VLSI devices, FPGAs in particular
due to their run-time reconfigurability. At the same time, vulnerability of FPGAs to
device-level attacks in the increasing cyber and hardware threat environment is also
quadrupling as the susceptible reliability realm opens door for the rogue elements to
intervene. Insertion of highly stealthy and malicious circuitry, called hardware
Trojans, in FPGAs is one of such malicious interventions. On the one hand where
such attacks/interventions adversely affect the security ambit of these devices, they
also undermine their reliability substantially. Hitherto, the security and reliability are
treated as two separate entities impacting the FPGA health. This has resulted in
fragmented solutions that do not reflect the true state of the FPGA operational and
functional readiness, thereby making them even more prone to hardware attacks.
The recent episodes of Spectre and Meltdown vulnerabilities are some of the key
examples. This research addresses these concerns by adopting an integrated
approach and investigating the FPGA security and reliability as two inter-dependent
entities with an additional dimension of health estimation/ prognostics. The design
and implementation of a small footprint frequency and threshold voltage-shift
detection sensor, a novel hardware Trojan, and an online transistor dynamic scaling
circuitry present a viable FPGA security scheme that helps build a strong
microarchitectural level defence against unscrupulous hardware attacks. Augmented
with an efficient Kernel-based learning technique for FPGA health
estimation/prognostics, the optimal integrated solution proves to be more
dependable and trustworthy than the prevalent disjointed approach.Samie, Mohammad (Associate)PhD in Transport System