Edge-adaptive spatial video de-interlacing algorithms based on fuzzy logic

Since the human visual system is especially sensitive to image edges, edge-dependent spatial interpolators have been proposed in literature as a means of successfully restoring edges while avoiding the staircase effect of linear spatial algorithms. This paper addresses the application of video de-interlacing, which constitutes an indispensable stage in video format conversion. Classic edge-adaptive de-interlacing algorithms introduce annoying artifacts when the edge directions are evaluated incorrectly. This paper presents two ways of exploiting fuzzy reasoning to reinforce edges without an excessive increase in computational complexity. The performance of the proposed algorithms is analyzed by de-interlacing a wide set of test sequences. The study compares the two proposals both with each other and with other edge-adaptive de-interlacing methods reported in the recent literatur

Fuzzy motion adaptive algorithm and its hardware implementation for video de-interlacing

Interlacing techniques were introduced in the early analog TV transmission systems as an efficient mechanism capable of halving the video bandwidth. Currently, interlacing is also used by some modern digital TV transmission systems, however, there is a problem at the receiver side since the majority of modern display devices require a progressive scanning. De-interlacing algorithms convert an interlaced video signal into a progressive one by performing interpolation. To achieve good de-interlacing results, dynamical and local image features should be considered. The gradual adaptation of the de-interlacing technique as a function of the level of motion detected in each pixel is a powerful method that can be carried out by means of fuzzy inference. The starting point of our study is an algorithm that uses a fuzzy inference system to evaluate motion locally (FMA algorithm). Our approach is based on convolution techniques to process a fuzzy rulebase for motion-adaptive de-interlacing. Different strategies based on bi-dimensional convolution techniques are proposed. In particular, the algorithm called 'single convolution algorithm' introduces significant advantages: a more accurate measurement of the level of motion using a matrix of weights, and a unique fuzzification process after the global estimation, which reduces the computational cost. Different architectures for the hardware implementation of this algorithm are described in VHDL language. The physical realization is carried out on a RC100 Celoxica FPGA development board. © 2010 Elsevier B.V.Comunidad Europea FP7-INFSO-ICT-248858Gobierno de España TIN2005-08943-C02-01 y TEC2008-04920Junta de Andalucía P08-TIC-0367

Implementing video compression algorithms on reconfigurable devices

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder

Implementation of Edge Dependent Interpolation Based De-Interlacer on FPGA

24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEYWOS: 000391250900025Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study.IEEE, Bulent Ecevit Univ, Dept Elect & Elect Engn, Bulent Ecevit Univ, Dept Biomed Engn, Bulent Ecevit Univ, Dept Comp Eng

Implementation of edge dependent interpolation based de-interlacer on FPGA [Kenar Bagimli Ara Degerleme Yöntemi Kullanarak De-Interlacer Işleminin FPGA Tabanli Gerçeklenmesi]

24th Signal Processing and Communication Application Conference, SIU 2016 -- 16 May 2016 through 19 May 2016 -- -- 122605Interlacing technique aims to lower the costs of high definition video systems by reducing the data amount sent to receiver unit. Regeneration of image at the receiver unit is an important point of interlacing method. In this study, regeneration (de-interlacing) of frames that are sent to receiver unit is implemented by using edge dependent interpolation method. The method is implemented using VHDL on Altera Cyclone-II FPGA. The method avoids reading of redundant data which yields to reduced operation time. Implementation occupies only %3 of the FPGA that is used in this study. © 2016 IEEE