3-D statistical simulation comparison of oxide reliability of planar MOSFETs and FinFET

New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design. © 2013 IEEE.published_or_final_versio

Impact of random dopant fluctuations on trap-assisted tunnelling in nanoscale MOSFETs

In this paper we introduce a novel simulation approach for the analysis of statistical variability in the trap-assisted tunnelling (TAT) gate leakage current in ultra-scaled MOSFETs. It accounts for the stochastic nature of trapping/emission dynamics underlying TAT current, and enables the simulation of TAT in the time domain. We demonstrate that random dopant fluctuations induce significant variability in the TAT gate leakage and investigate the details of its origin. Finally we present TAT current characteristics for different dopants configurations. © 2012 Elsevier Ltd. All rights reserved.Link_to_subscribed_fulltex