2,820 research outputs found
Methodology for standard cell compliance and detailed placement for triple patterning lithography
As the feature size of semiconductor process further scales to sub-16nm
technology node, triple patterning lithography (TPL) has been regarded one of
the most promising lithography candidates. M1 and contact layers, which are
usually deployed within standard cells, are most critical and complex parts for
modern digital designs. Traditional design flow that ignores TPL in early
stages may limit the potential to resolve all the TPL conflicts. In this paper,
we propose a coherent framework, including standard cell compliance and
detailed placement to enable TPL friendly design. Considering TPL constraints
during early design stages, such as standard cell compliance, improves the
layout decomposability. With the pre-coloring solutions of standard cells, we
present a TPL aware detailed placement, where the layout decomposition and
placement can be resolved simultaneously. Our experimental results show that,
with negligible impact on critical path delay, our framework can resolve the
conflicts much more easily, compared with the traditional physical design flow
and followed layout decomposition
Layout Decomposition for Quadruple Patterning Lithography and Beyond
For next-generation technology nodes, multiple patterning lithography (MPL)
has emerged as a key solution, e.g., triple patterning lithography (TPL) for
14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this
paper, we propose a generic and robust layout decomposition framework for QPL,
which can be further extended to handle any general K-patterning lithography
(K4). Our framework is based on the semidefinite programming (SDP)
formulation with novel coloring encoding. Meanwhile, we propose fast yet
effective coloring assignment and achieve significant speedup. To our best
knowledge, this is the first work on the general multiple patterning
lithography layout decomposition.Comment: DAC'201
Case studies on lithography-friendly vlsi circuit layout
Moore’s Law has driven a continuous demand for decreasing feature sizes used
in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions
offered by lithography hardware. Currently, a light wavelength of 193nm is being used
to print sub-65nm features. This introduces process variations which cause mismatches
between desired and actual wafer feature sizes. However, the layout which affects the
printability of a circuit can be modified in a manner which can make it more
lithography-friendly.
In this work, we intend to implement these modifications as a series of
perturbations on the initial layout generated by the CAD tool for the circuit. To
implement these changes we first calculate the feature variations offline on the
boundaries of all possible standard cell pairs used in the circuit layout and record them in
a Look-Up Table (LUT). After the CAD tool generates the initial placement of the
circuit, we use the LUT to estimate the variations on the boundaries of all the standard
cells. Depending on the features which may have the highest feature variations we assign
a cost to the layout and our aim is now to reduce the cost of the layout after
implementing perturbations which could be a simple cell flip or swap with a neighboring
cell. The algorithm used to generate a circuit placement with a low cost is Simulated
Annealing which allows a high probability for a solution with a higher cost to be
selected during the initial iterations and as time goes on it tends closer to the greedy
algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of
wirelength, vias and routing congestion.
We validate our procedure on ISCAS85 benchmark circuits by simulating dose
and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of
greater 20% in the number of instances with the highest cell boundary feature variations.
The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2-
7.8% respectively for different circuits. The routing congestion by and large remains
unaffected
A High-Performance Triple Patterning Layout Decomposer with Balanced Density
Triple patterning lithography (TPL) has received more and more attentions
from industry as one of the leading candidate for 14nm/11nm nodes. In this
paper, we propose a high performance layout decomposer for TPL. Density
balancing is seamlessly integrated into all key steps in our TPL layout
decomposition, including density-balanced semi-definite programming (SDP),
density-based mapping, and density-balanced graph simplification. Our new TPL
decomposer can obtain high performance even compared to previous
state-of-the-art layout decomposers which are not balanced-density aware, e.g.,
by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13).
Furthermore, the balanced-density version of our decomposer can provide more
balanced density which leads to less edge placement error (EPE), while the
conflict and stitch numbers are still very comparable to our
non-balanced-density baseline
Effects of grid-placed contacts on circuit performance
The impact of grid-placed contacts on application-specific integrated circuit (ASIC) performance is studied. Although snapping contacts to grid adds restrictions during layout design, smaller circuit area can be achieved by careful selection of the grid pitch, raising the lower limit of transistor width, applying double exposure, and shrinking the minimum contact pitch enabled by more effective application of resolution enhancement technologies. The technique is demonstrated on the contact level of 250-nm standard cells with the minimum contact pitch shrunk by 10%. The area change of 84 cells ranges from -20% to 25% with a median decrease of 5%. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2% respectively. Delay and power consumption are also estimated to decrease with area.published_or_final_versio
Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates
The practicability and methodology of applying resolution-enhancement- technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the over-all circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from -4.2 to -15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from -16.2 to +2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Pnoto-Optical Instrumentation Engineers.published_or_final_versio
Standard cell layout with regular contact placement
The practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.published_or_final_versio
Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer. (C) 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)Peer ReviewedPostprint (author’s final draft
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SiOx-based resistive switching memory integrated in nanopillar structure fabricated by nanosphere lithography
textA highly compact, one diode-one resistor (1D-1R) SiOx-based resistive switching memory device with nano-pillar architecture has been achieved for the first time using nano-sphere lithography. The average nano-pillar height and diameter are 1.3 ÎĽm and 130 nm, respectively. Low-voltage electroforming using DC bias and AC pulse response in the 50ns regime demonstrate good potential for high-speed, low-energy nonvolatile memory. Nano-sphere deposition, oxygen-plasma isolation, and nano-pillar formation by deep-Si-etching are studied and optimized for the 1D-1R configurations. Excellent electrical performance, data retention and the potential for wafer-scale integration are promising for future non-volatile memory applications.Materials Science and Engineerin
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