Gold free ohmic contacts for III-V MOSFET devices

Over the past forty years the development of CMOS has been able to follow Moore’s law using planar silicon technology. However, this technology is reaching its limits as the density of transistors has a significant impact on the power dissipation in an integrated circuit. Alternative channel materials and device architectures will then be required in the future to reduce the power consumption of transistors. The development of CMOS technology with high mobility channel materials, specifically Ge for pMOS and III-V materials for nMOS, was the aim of the European Union FP7 funded Duallogic consortium, of which this project was part. The experimental work at the University of Glasgow was the III-V compound semiconductor MOSFET, in particular the study of Si processing compatible source/drain contacts to III-V MOSFET devices with InxGa1-xAs channel materials, which was an important aspect of this thesis. Another area investigated in this thesis is the impact of current crowding effects on source/drain contact resistance by aggressive scaling of devices. During this thesis, optimisation of a PdGe-based ohmic contact to buried channel device material with a In0.75GaAs channel led to a contact resistance of 0.15Ohm.mm compared to 1Ohm.mm in previous work by R. Hill. The PdGe-based contact also proved to be scalable in both vertical and lateral dimensions. This scaled structure was then integrated in a surface channel MOSFET device with 1μm access regions and gate lengths varying from 100nm to 20μm. The performance of the devices with 20μm gate lengths was then compared to devices with a NiGeAu based ohmic contact. An increase in RC, 1.82Ohm.mm vs. 0.94Ohm.mm, and Ron, 11.1Ohm.mm vs. 8.55Ohm.mm, was observed in the PdGe-based contact, which resulted in a decrease in gm, 92.3mS/mm vs. 103mS/mm, and Id,sat, 103mA/mm vs. 122mA/mm. However, further optimisation of the PdGe-based ohmic contact showed promising results with a contact resistance of 0.45Ohm.mm. The novel test structure is the first test structure, which makes direct contact to III-V material, with critical dimensions below the transfer length. This structure is able to experimentally observe the current crowding effects and allows for the extraction of the sheet resistance underneath the contact and a more accurate extraction of the specific contact resistivity. This offers a significant insight into the impact of the sheet resistance underneath the contact and the role it plays

Validation by Measurements of a IC Modeling Approach for SiP Applications

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi

The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes

Voltage noise analysis with ring oscillator clocks

Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise as technology scales down and power density increases. However, their effectiveness highly depends on the design parameters of the PDN, power consumption patterns of the system and spatial locality of the ROCs within the clock domains. This paper analyzes the impact of the PDN parameters and ROC location on the robustness to voltage noise. The capability of reacting instantaneously to unpredictable voltage droops makes ROCs an attractive solution, which allows to reduce the amount of decoupling capacitance without downgrading performance. Tolerance to voltage noise and related benefits can be increased by using multiple ROCs and reducing the size of the clock domains. The analysis shows that up to 83% of the margins for voltage noise and up to 27% of the leakage power can be reduced by using local ROCs.Peer ReviewedPostprint (author's final draft

Numerical Simulation of III-V Solar Cells Using D-AMPS

Numerical simulation of devices plays a crucial role in their design, performance prediction, and comprehension of the fundamental phenomena ruling their operation. Here, we present results obtained using the code D-AMPS-1D, that was conveniently modified to consider the particularities of III-V solar cell devices. This work, that is a continuation of a previous paper regarding solar cells for space applications, is focused on solar cells structures than find application for terrestrial use under concentrated solar illumination. The devices were fabricated at the Solar Energy Institute of the Technical University of Madrid (UPM). The first simulations results on InGaP cells are presented. The influence of band offsets and band bending at the window-emitter interface on the quantum efficiency was studied. A remarkable match of the experimental quantum efficiency was obtained. Finally, numerical simulation of single junction n-p InGaP-Ge solar cells was performed

Power Beacon-Assisted Millimeter Wave Ad Hoc Networks

Deployment of low cost power beacons (PBs) is a promising solution for dedicated wireless power transfer (WPT) in future wireless networks. In this paper, we present a tractable model for PB-assisted millimeter wave (mmWave) wireless ad hoc networks, where each transmitter (TX) harvests energy from all PBs and then uses the harvested energy to transmit information to its desired receiver. Our model accounts for realistic aspects of WPT and mmWave transmissions, such as power circuit activation threshold, allowed maximum harvested power, maximum transmit power, beamforming and blockage. Using stochastic geometry, we obtain the Laplace transform of the aggregate received power at the TX to calculate the power coverage probability. We approximate and discretize the transmit power of each TX into a finite number of discrete power levels in log scale to compute the channel and total coverage probability. We compare our analytical predictions to simulations and observe good accuracy. The proposed model allows insights into effect of system parameters, such as transmit power of PBs, PB density, main lobe beam-width and power circuit activation threshold on the overall coverage probability. The results confirm that it is feasible and safe to power TXs in a mmWave ad hoc network using PBs.Comment: This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl