Random Discrete Dopant Induced Variability in Negative Capacitance Transistors

In this work we investigate the impact of random discrete dopants (RDD) induced statistical variability in ferroelectric negative capacitance field effect transistors (NCFETs). We couple the 3D `atomistic' statistical device simulator GARAND with the Landau - Khalatnikov equation of the ferroelectric for this study. We found that the negative capacitance effect provided by the ferroelectric layer can lead to suppression of the RDD induced variability in the threshold voltage (Vt), OFF-current (IOFF), and ON-current (ION). This immunity to RDD induced variability increases with increase in the ferroelectric thickness

Modeling and Simulation of Negative Capacitance MOSFETs

The current and voltage characteristics of a MOSFET device are maily characterized by the source to channel barrier which is controlled by the gate voltage. The Boltazmann statistics which govern the number of carriers that are able to cross the barrier indicates that to increase the current by a decade, atleast 60 mV of rise in gate voltage is required. As a result of this limitation, the threshold voltage of modern MOSFETs cannot be less than about 0.3 V for an ION to IOFF ratio of 5 decades. This has put a fundamental bottleneck in voltage downscaling increasing the power consumption in modern IC based chips with billions of transistors. Sayeef Salahuddin and Supriyo Dutta proposed the idea of including ferroelectric in MOSFET gate stack which allows an internal voltage ampli�cation at the MOSFET channel which can be used to achieve a smaller subthreshold swing which would further reduce the power consumption of the devices. In this thesis we have undertaken a simulation based study of such devices to study how the inclusion of negative capacitance ferroelectrics leads changes in various device characteristics. Initially we have taken a compact modeling based approach to study device characteristics in latest industry standard FinFET devices. For this purpose we have used the BSIM-CMG Verilog A model and modi�ed the model appropriately to include the e�ect of negative capacitance ferroelectric in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can indeed give a subthreshold swing lesser than 60 mV/dec. Further other interesting properties like negative output resistance and drain induced barrier rising are observed. Using the compact models developed above, we have analyzed some simple circuits with NC devices. Initially an inverter shows a hysteresis in the transfer characteristics. This can be attributed to negative di�erential resistance. Ring oscillator analysis shows that RO frequency for NC devices is lesser than that of regular devices due to enhanced gate capacitance and slower response of ferroelectrics. Scaling analysis has been performed to see the performance of NC devices in future technologies. For this we used TCAD analysis coupled with Landau Khalatnikov equation. This analysis shows that NC devices are more e�ective in suppressing short channel e�ects like DIBL and can hence be used for further downscaling of the devices. Finally we develop models to take into account the multidomain Landau equations for ferroelec- tric into account. We have performed such an analysis for a ferroelectric resistor series network. A similar analysis is performed for short channel double gate MOSFET without inter layer metal be- tween ferroelectric and the internal MOS device. This analysis showed that coupling factor between ferroelectric domains plays an important role in the device characteristics

III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2

β\beta-Ga2_2O3_3 Nano-membrane Negative Capacitance Field-effect Transistor with Steep Subthreshold Slope for Wide Bandgap Logic Applications

Steep-slope $\beta$-Ga$_2$O$_3$ nano-membrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate voltage sweeps with a minimum value of 34.3 mV/dec at reverse gate voltage sweep and 53.1 mV/dec at forward gate voltage sweep at $V_{DS}$=0.5 V. Enhancement-mode operation with threshold voltage ~0.4 V is achieved by tuning the thickness of $\beta$-Ga$_2$O$_3$ membrane. Low hysteresis of less than 0.1 V is obtained. The steep-slope, low hysteresis and enhancement-mode $\beta$-Ga$_2$O$_3$ NC-FETs are promising as nFET candidate for future wide bandgap CMOS logic applications.Comment: 21 pages, 5 figure

적층 나노시트 구조의 음의 정전용량 전계 효과 트랜지스터

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 최우영.The development of integrated circuit (IC) technology has continued to improve speed and capacity through miniaturization of devices. However, power density is increasing rapidly due to the increasing leakage current as miniaturization advances. Although the remarkable advancement of process technology has allowed complementary-metal-oxide-semiconductor (CMOS) technology to consistently overcome its constraints, the physical limitations of the metal-oxide-semiconductor field-effect transistor (MOSFET) are unmanageable. Accordingly, research on logic device is being divided into a CMOS-extension and a beyond-CMOS. CMOS-extension focuses on the gate-all-around field-effect transistors (GAAFETs) which is a promising architecture for future CMOS thanks to the excellent electrostatic gate controllability. Particularly, nanosheet (NS) architecture with high current drivability required in ICs, is the most promising. However, NS GAAFET has a trade-off relation between the controllability and the drivability, which requires the necessity of a higher-level effective oxide thickness (EOT) scaling for further scaling of NS GAAFET. On the other hand, beyond-CMOS mainly focuses on developing devices with novel mechanisms to overcome the MOSFETs' physical limits. Among several candidates, negative capacitance field-effect transistors (NCFETs) with exceptional CMOS compatibility and current drivability are highlighted as future logic devices for low-power, high-performance operation. Although the NCFET utilizing the negative capacitance (NC) effect of a ferroelectric has been demonstrated theoretically by the Landau model, it is challenging to be implemented due to the fact that stabilized NC and sub-thermionic subthreshold swing (SS) are incompatible. In this dissertation, a GAA NCFET that maintains a stable capacitance boosting by NC effect and exhibits high performance is demonstrated. A ferroelectric-antiferroelectric mixed-phase hafnium-zirconium-oxide (HZO) thin film was introduced, whose effect was confirmed by capacitors and FET experiments. Furthermore, the mixed-phase HZO was demonstrated on a stacked nanosheet gate-all-around (stacked NS GAA) structure, the advanced CMOS technology, which exhibits a superior gate controllability as well as a satisfactory drivability for ICs. The hysteresis-free stable NC operation with the superior performance was confirmed in NS GAA NCFET. The improved SS and on-current (Ion) compared to MOSFETs fabricated in the same manner were validated, and its feasibility as a low-power, high-performance logic device was proven based on a variety of figure of merits.집적회로 기술의 발전은 소자의 소형화를 통한 속도 및 용량의 향상을 위해 발전을 거듭해왔다. 그러나 소형화를 거듭할수록 증가하는 누설전류의 문제로 전력 밀도가 급격하게 증가하고 있다. 상보형 금속-산화막-반도체(CMOS) 기술은 눈부신 공정기술의 성장에 힘입어 한계를 끊임없이 극복해왔으나, 기존의 금속-산화막-반도체 전계-효과-트랜지스터(MOSFET)의 물리적 한계는 극복할 수 없는 문제이다. 이에 따라 논리 반도체에 관한 연구는 CMOS를 연장하는 방향과 CMOS를 뛰어넘는 방향으로 나뉘어 진행되고 있다. CMOS를 연장하는 방향은 뛰어난 정전기적 게이트 장악력을 갖는 차세대 CMOS 구조로 유망한 게이트-올-어라운드 전계-효과-트랜지스터(GAAFET)에 관한 연구가 주를 이룬다. 특히 높은 전류 구동력을 가질 수 있는 나노시트(NS) 구조가 가장 유망한데, 게이트 장악력이 전류 구동력과 상충된다는 단점이 있다. 이에 따라 NS GAAFET 기술을 위해서는 더 높은 수준의 유효산화막두께 (EOT) 스케일링이 필수적이다. 한편, CMOS를 뛰어넘는 방향의 연구는 MOSFET의 물리적 한계를 극복하기 위해 새로운 메커니즘을 갖는 소자를 개발하는 방향으로 이루어진다. 다양한 후보군 중 CMOS 호환성과 전류 구동능력이 뛰어난 음의 정전용량 전계-효과-트랜지스터(NCFET)이 저전력, 고성능 동작을 위한 미래 CMOS 소자로 각광받고 있다. 강유전체의 음의 정전용량 (NC) 효과를 이용한 NCFET은 Landau 모델에 의해 이론적으로 증명되었으나, 열역학적으로 안정한 상태와 60 mV/dec 이하의 문턱전압-이하-기울기(SS)를 동시에 구현하기 불가능하다는 문제가 있다. 본 학위논문에서는 안정한 정전용량 향상 특성을 가지며 높은 성능을 갖는 NS GAA NCFET을 구현하였다. 강유전체(ferroelectric)-반강유전체(antiferroelectric) 혼합상(mixed-phase) 하프늄-지르코늄-옥사이드(HZO) 박막의 정전용량 향상 효과를 커패시터 및 FET 제작을 통해 효과를 검증하였다. 또한 높은 게이트 장악력을 가지며 집적회로에서 요구하는 전류 구동력을 만족시킬 수 있는 적층형 나노시트 게이트-올-어라운드(stacked NS GAA) 구조에 혼합상 NC 박막을 적용한 FET을 시연하고 성능의 우수성을 확인하였다. 동일하게 제작된 MOSFET 대비 향상된 SS와 구동 전류(Ion)를 확인하였고, 다양한 성능 지수를 토대로 저전력, 고성능 로직 소자로서의 타당성을 검증하였다.Abstract i Contents iv List of Table vii List of Figures viii Chapter 1 Introduction 1 1.1 Power and Area Scaling Challenges 1 1.2 Nanosheet Gate-All-Around FETs 5 1.2.1 Gate-All-Around FETs 5 1.2.2 Nanosheet GAAFETs 6 1.3 Negative Capacitance FETs 11 1.3.1 Negative Capacitance in Ferroelectric Materials 11 1.3.2 Negative Capacitance for Steep Switching Devices 14 1.3.3 Stable NC vs. Sub-thermionic SS 17 1.4 Scope and Organization of Dissertation 21 Chapter 2 Stacked NS GAA NCFET with Ferroelectric-Antiferroelectric-Mixed-Phase HZO 22 2.1 Mixed-Phase HZO for Capacitance Boosting 22 2.2 NS GAA NCFET using Mixed-Phase HZO 25 Chapter 3 HZO ALD Stack Optimization 28 3.1 Metal-Ferroelectric-Interlayer-Silicon (MFIS) / MFM Capacitors 29 3.1.1 Fabrication of MFIS Capacitors 29 3.1.2 Electrical Characteristics of MFIS / MFM Capacitors 33 3.2 SOI Planar NCFETs 38 3.2.1 DC Measurements 38 3.2.2 Direct Capacitance Measurements 47 3.2.3 Speed Measurements 49 Chapter 4 Device Fabrication of Stacked NS GAA NCFET 51 4.1 Initial Process Flow of NS GAA NCFET 52 4.2 Process Issues and Solution 56 4.2.1 External Resistance 56 4.2.2 TiN Gate Sidewall Spacer 60 4.2.3 Unintentionally Etched Sacrificial Layer 65 4.2.4 Discussions 68 4.3 Channel Release Process 69 4.3.1 Consideration in Channel Release Process 69 4.3.2 Methods for SiGe Selective Etching 72 4.3.3 SiGe Selective Etching using Carboxylic Acid Solution 75 4.4 Revised Process of NS GAA NCFET 78 Chapter 5 Electrical Characteristics of Fabricated NS GAA NCFET 84 5.1 DC Characteristics 85 5.1.1 NS GAA NCFET vs. Planar SOI NCFET 85 5.1.2 Performance Enhancement of NS GAA NCFET 88 5.1.3 Performance Evaluation 96 5.2 Operating Temperature Properties 99 Chapter 6 Conclusion 102 Bibliography 105 초 록 115박