A Special Purpose Architecture for Finite Element Analysis

The analysis of aerospace structures by the finite element method consumes considerable computer time. The cost of this resource and the designer's desire to have rapid feedback concerning such questions as the effect of a change in loading of the structure or in a parameter of some structural material led to the design of a special purpose parallel computing system for finite element analysis. As a special purpose computer, the architecture of this finite element computer is closely tied to computational aspects of the particular problem. Various aspects of an MIMD array of microprocessors are related to the requirements of the class of finite element analysis problems which it is intended to solve

Design, development, and flight test of a demonstration advanced avionics system

Ames Research Center initiated a program in 1975 to provide the critical information required for the design of integrated avionics suitable for general aviation. The program emphasized the use of data busing, distributed microprocessors, shared electronic displays and data entry devices, and improved functional capability. Design considerations included cost, reliability, maintainability, and modularity. As a final step, a demonstration advanced avionics system (DAAS) was designed, built, and flight tested in a Cessna 402, twin engine, general aviation aircraft. A functional description of the DAAS, including a description of the system architecture, is presented and the program and flight test results are briefly reviewed

Software modifications to the Demonstration Advanced Avionics Systems (DAAS)

Critical information required for the design of integrated avionics suitable for generation aviation is applied towards software modifications for the Demonstration Advanced Avionics System (DAAS). The program emphasizes the use of data busing, distributed microprocessors, shared electronic displays and data entry devices, and improved functional capability. A demonstration advanced avionics system (DAAS) is designed, built, and flight tested in a Cessna 402, twin engine, general aviation aircraft. Software modifications are made to DAAS at Ames concurrent with the flight test program. The changes are the result of the experience obtained with the system at Ames, and the comments of the pilots who evaluated the system

High–Speed Data Transmission Subsystem of the SEOSAR/PAZ Satellite

This paper analyzes a digital interface and bus system modeling and optimization of the SEOSAR/PAZ Earth Observation satellite. The important part of the satellite is an X–band Synthetic Aperture Radar instrument that integrates 384 Transmit/Receive Modules located in 12 antenna panels 7.5 m away from the central processor and controlled by a synchronous 10 Mbps bidirectional serial protocol. This type of mid–range point–to–multipoint transmission is affected by bit errors due to crosstalk, transmission line attenuation and impedance mismatches. The high–speed data communication network has been designed to optimize the transmission by using a simulation model of the data distribution system which takes into account the worst–case scenario and by developing a lab–scaled prototype which exhibits BER of 10-11 for an interfering signal of 10 Vpp. The result is a point–to–multipoint bidirectional transmission network optimized in both directions with optimal values of loads and equalization resistors. This high–speed data transmission subsystem provides a compact design through a simple solution

A user's guide for the signal processing software for image and speech compression developed in the Communications and Signal Processing Laboratory (CSPL), version 1

A complete documentation of the software developed in the Communication and Signal Processing Laboratory (CSPL) during the period of July 1985 to March 1986 is provided. Utility programs and subroutines that were developed for a user-friendly image and speech processing environment are described. Additional programs for data compression of image and speech type signals are included. Also, programs for the zero-memory and block transform quantization in the presence of channel noise are described. Finally, several routines for simulating the perfromance of image compression algorithms are included

The General Purpose Interface Bus

The General Purpose Interface Bus, as defined by the IEEE Standard, deals with systems that require digital data to be transferred between a group of instruments. An overview of this standard is presented which summarizes the interface\u27s capabilities, functions and versatility by explaining the basic interface concepts. In addition, a GPIB testing application and a GPIB related design example are presented and investigated

Measurement of linear position using a magnetostrictive wire

Bibliography: pages 114-115.This thesis reports the details of construction and testing of a linear position measuring device and subsequent experimentation with the system. The design goals established were to construct a measuring device using established TTL devices, proven interfaces, ultra-reliable noise-clean, circuits, inexpensive components and to be based on transmission of magnetostrictively generated pulses in nickel wire. In addition it was to be able to operate in a harsh environment (e.g. underwater) where alternative devices would not function. While an accuracy objective was not established, it was hoped to be able to push accuracy near to the theoretical resolution. A. prototype measuring device was constructed consisting of a stretched nickel wire threaded through a transmitting coil and three receiving coils together with transmitting, receiving, timing and interface circuitry. The nickel wire was mounted on an optical bench with one receiving coil mounted to a moveable trolley. This configuration facilitated calibration and testing. The system was interfaced to a microcomputer via an IEEE 488 GPIB controller and calibration, testing and position appropriate computer programmes

The RIT IEEE-488 buffer design

This document describes the design of an NMOS ASIC used to control an RIT IEEE-488 Buffer previously designed by the author. Past designs used discrete components to implement an asynchronous controller and a synchronous, one-hot controller. The present design utilizes a multiple controller architecture incorporated within the ASIC. The ASIC is used to control bus protocol, bus transceivers, and memory. At power-up, the buffer configures itself as an active listener on the bus and waits for a talker to initiate communication. The buffer accepts a data file (a plot file for example) from the talker, then takes control of the bus, addresses a listener, transfers the stored data to the listener, unaddresses the listener, releases the bus, and finally, reassumes the active listener configuration. The RIT IEEE-488 buffer can realize time savings for a user in a controllerless system. The buffer accepts data from a talker in a matter of seconds and then takes on the chore of driving a slow listener. Thus, the talker is returned quickly to the operator for further use. At present, the buffer isn\u27t queueable - it cannot accept another data file until it completes the transfer of the present file. The author has also added five nmos cells (schematic/layout) into the \u27/user/pub\u27 directory on the Apollo workstations in the Computer Engineering Department\u27s VLSI LAB at RIT. Cell names are VSCLK, SYNC, CLOCK_GEN_STACK, PAD_TRISTATE, and PAD_TRISTATE_BUFFERED. All five cells have been simulated and successfully run through DRC, ERC, and LVS checks

Study to determine potential flight applications and human factors design guidelines for voice recognition and synthesis systems

A study was conducted to determine potential commercial aircraft flight deck applications and implementation guidelines for voice recognition and synthesis. At first, a survey of voice recognition and synthesis technology was undertaken to develop a working knowledge base. Then, numerous potential aircraft and simulator flight deck voice applications were identified and each proposed application was rated on a number of criteria in order to achieve an overall payoff rating. The potential voice recognition applications fell into five general categories: programming, interrogation, data entry, switch and mode selection, and continuous/time-critical action control. The ratings of the first three categories showed the most promise of being beneficial to flight deck operations. Possible applications of voice synthesis systems were categorized as automatic or pilot selectable and many were rated as being potentially beneficial. In addition, voice system implementation guidelines and pertinent performance criteria are proposed. Finally, the findings of this study are compared with those made in a recent NASA study of a 1995 transport concept

A graphics subsystem retrofit design for the bladed-disk data acquisition system

A graphics subsystem retrofit design for the turbojet blade vibration data acquisition system is presented. The graphics subsystem will operate in two modes permitting the system operator to view blade vibrations on an oscilloscope type of display. The first mode is a real-time mode that displays only gross blade characteristics, such as maximum deflections and standing waves. This mode is used to aid the operator in determining when to collect detailed blade vibration data. The second mode of operation is a post-processing mode that will animate the actual blade vibrations using the detailed data collected on an earlier data collection run. The operator can vary the rate of payback to view differring characteristics of blade vibrations. The heart of the graphics subsystem is a modified version of AMD's ""super sixteen'' computer, called the graphics preprocessor computer (GPC). This computer is based on AMD's 2900 series of bit-slice components