Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks

Mixed-criticality models are an emerging paradigm for the design of real-time systems because of their significantly improved resource efficiency. However, formal mixed-criticality models have traditionally been characterized by two impractical assumptions: once \textit{any} high-criticality task overruns, \textit{all} low-criticality tasks are suspended and \textit{all other} high-criticality tasks are assumed to exhibit high-criticality behaviors at the same time. In this paper, we propose a more realistic mixed-criticality model, called the flexible mixed-criticality (FMC) model, in which these two issues are addressed in a combined manner. In this new model, only the overrun task itself is assumed to exhibit high-criticality behavior, while other high-criticality tasks remain in the same mode as before. The guaranteed service levels of low-criticality tasks are gracefully degraded with the overruns of high-criticality tasks. We derive a utilization-based technique to analyze the schedulability of this new mixed-criticality model under EDF-VD scheduling. During runtime, the proposed test condition serves an important criterion for dynamic service level tuning, by means of which the maximum available execution budget for low-criticality tasks can be directly determined with minimal overhead while guaranteeing mixed-criticality schedulability. Experiments demonstrate the effectiveness of the FMC scheme compared with state-of-the-art techniques.Comment: This paper has been submitted to IEEE Transaction on Computers (TC) on Sept-09th-201

Extended class of linear feedback shift registers

Shift registers with linear feedback are frequently used. They owe their popularity to very well developed theoretical base. Registers with feedback of prime polynomials are of particular practical importance. They are willingly applied as test sequence generators and test response compactors. The article presents an attempt to extend the class of registers with linear feedback. Basing on the formal description of the register, the algorithms of register transformation are proposed. It allows to obtain the registers with equivalent graphs.[1] I. Gosciniak, “Linear Registers with Mixed Feedback, in Polish; Rejestry liniowe z mieszanym sprzȩżeniem zwrotnym,” Pomiary Automatyka Kontrola, no. 1, pp. 4–6, 1996.[2] K. Iwasaki, “Analysis and proposal of signature circuits for LSI testing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 84–90, 1988.[3] L.-T. Wang, N. Touba, R. Brent, H. Xu, and H. Wang, “On Designing Transformed Linear Feedback Shift Registers with Minimum Hardware Cost – Technical Report,” Computer Engineering Research Center Department of Electrical & Computer Engineering The University of Texas at Austin, 2011.[4] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Method for Synthesizing Linear Finite State Machines,” U.S. Patent, No. 6,353,842, 2002.[5] I. Gosciniak, “Equivalent Form of Linear Feedback Shift Registers,” in XIXth National Conference Circuit Theory and Eletronic Networks, 1996, pp. 115–120.[6] L. Alaus, D. Noguet, and J. Palicot, “A Reconfigurable LFSR for Tristandard SDR Transceiver, Architecture and Complexity Analysis,” in Digital System Design Architectures, Methods and Tools, 2008. DSD ’08. 11th EUROMICRO Conference on. IEEE Computer Society, 2008, pp. 61–67.[7] R. Ash, Information Theory. John Wiley & Sons, 1967.[8] M. Kopec, “Can Nonlinear Compactors Be Better than Linear Ones?” IEEE Trans. Comput., no. 11, pp. 1275–1282, 1995.[9] A. Gucha and L. Kinney, “Relating the Cyclic Behaviour of Linear Intrainverted Feedback shift Registers,” IEEE Transactions on Computers, vol. 41, no. 9, pp. 1088–1100, 1992

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Online and Offline BIST in IP-Core Design

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

Distributed PC Based Routers: Bottleneck Analysis and Architecture Proposal

Recent research in the different functional areas of modern routers have made proposals that can greatly increase the efficiency of these machines. Most of these proposals can be implemented quickly and often efficiently in software. We wish to use personal computers as forwarders in a network to utilize the advances made by researchers. We therefore examine the ability of a personal computer to act as a router. We analyze the performance of a single general purpose computer and show that I/O is the primary bottleneck. We then study the performance of distributed router composed of multiple general purpose computers. We study the performance of a star topology and through experimental results we show that although its performance is good, it lacks flexibility in its design. We compare it with a multistage architecture. We conclude with a proposal for an architecture that provides us with a forwarder that is both flexible and scalable.© IEE

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

A Hierachical Infrastrucutre for SOC Test Management

HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

Adaptive Latency Insensitive Protocols

Latency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail

Online self-repair of FIR filters

Chip-level failure detection has been a target of research for some time, but today's very deep-submicron technology is forcing such research to move beyond detection. Repair, especially self-repair, has become very important for containing the susceptibility of today's chips. This article introduces a self-repair-solution for the digital FIR filter, one of the key blocks used in DSPs