Reduced basis method for source mask optimization

Image modeling and simulation are critical to extending the limits of leading edge lithography technologies used for IC making. Simultaneous source mask optimization (SMO) has become an important objective in the field of computational lithography. SMO is considered essential to extending immersion lithography beyond the 45nm node. However, SMO is computationally extremely challenging and time-consuming. The key challenges are due to run time vs. accuracy tradeoffs of the imaging models used for the computational lithography. We present a new technique to be incorporated in the SMO flow. This new approach is based on the reduced basis method (RBM) applied to the simulation of light transmission through the lithography masks. It provides a rigorous approximation to the exact lithographical problem, based on fully vectorial Maxwell's equations. Using the reduced basis method, the optimization process is divided into an offline and an online steps. In the offline step, a RBM model with variable geometrical parameters is built self-adaptively and using a Finite Element (FEM) based solver. In the online step, the RBM model can be solved very fast for arbitrary illumination and geometrical parameters, such as dimensions of OPC features, line widths, etc. This approach dramatically reduces computational costs of the optimization procedure while providing accuracy superior to the approaches involving simplified mask models. RBM furthermore provides rigorous error estimators, which assure the quality and reliability of the reduced basis solutions. We apply the reduced basis method to a 3D SMO example. We quantify performance, computational costs and accuracy of our method.Comment: BACUS Photomask Technology 201

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Design for Manufacturing in IC Fabrication: Mask Cost, Circuit Performance and Convergence

Ph.DDOCTOR OF PHILOSOPH

Resolution enhancement in mask aligner photolithography

Photolithographie ist eine unentbehrliche Technologie in der heutigen Mikrofabrikation integrierter elektronischer Schaltungen und optischer Komponenten auf verschiedenen Größenskalen. Die zugrundeliegende Aufgabe ist die Replikation der gewünschten Struktur, die kodiert ist in einer Photomaske, auf einem photolackbedeckten Wafer. In vergangenen Jahrzehnten gab es eine beeindruckende Weiterentwicklung photolithographischer Anlagen, was Auflösungen weit unterhalb eines Mikrometers ermöglicht. Das einfachste photolithographische Instrument ist der Maskenjustierbelichter, bei dem die Photomaske und der Wafer entweder in Kontakt oder in unmittelbare Nähe gebracht werden (Proximity-Modus), ohne zusätzliche optische Komponenten dazwischen. Vor über 50~Jahren eingeführt bleibt der Maskenjustierbelichter aufgrund seines wirtschaftlichen Betriebs das Instrument der Wahl für die Herstellung unkritischer Schichten, mit einer Auflösung von einigen Mikrometern im bevorzugten Proximity-Modus. Maskenjustierbelichter werden beispielsweise für die Herstellung von Mikrolinsen, lichtemittierende Dioden und mikromechanischen Systemen verwendet. Die erreichbare laterale räumliche Auflösung ist letztlich begrenzt durch die Beugung des Lichts an den Strukturen der Photomaske, was zu Verfälschungen der Abbildung auf dem Photolack führt. In dieser Arbeit entwickeln, präsentieren und diskutieren wir mehrere Technologien zur Auflösungsverbesserung für Maskenjustierbelichter im Proximity-Modus. Dies umfasst Photolithographie mit einer neuartigen Lichtquelle, die im tiefen Ultraviolett-Bereich emittiert, eine rigoros optimierte Phasenschiebermaske für periodische Strukturen, optische Proximity-Korrektur (Nahbereichskorrektur) angewandt auf nichtorthogonale Geometrien, und die Anwendung optischer Metaoberflächen als Photomasken. Eine Reduzierung der Wellenlänge verringert die Auswirkungen der Lichtbrechung und verbessert daher direkt die Auflösung, benötigt aber auch die Entwicklung geeigneter Konzepte für die Strahlformung und Homogenisierung der Beleuchtung. Wir diskutieren die Integration einer neuartigen Lichtquelle, ein frequenzvervierfachter Dauerstrichlaser mit einer Emissionswellenlänge von 193$\,$nm, in einem Maskenjustierbelichter. Damit zeigen wir erfolgreiche Prints von Teststrukturen mit einer Auflösung von bis zu 1,75$\,$µm bei einem Proximity-Abstand von 20$\,$µm. Bei Verwendung des selbstabbildenden Talboteffekts wird sogar eine Auflösung weit unterhalb eines Mikrometers für periodische Strukturen erzielt. Außerdem diskutieren wir die rigorose Simulation und Optimierung der Lichtausbreitung in und hinter Phasenschiebermasken, die unter schrägem Einfall belichtet werden. Mit einem optimierten Photomaskendesign kann dabei die Periode bei Belichtung unter drei diskreten Winkeln verkleinert abgebildet werden. Dies erlaubt es, Strukturen deutlich kleiner als ein Mikrometer abzubilden, wobei die Strukturen auf der Photomaske deutlich größer und damit einfacher herzustellen sind. Zudem betrachten wir eine Simulations- und Optimierungsmethode für die optische Proximity-Korrektur nicht-orthogonaler Strukturen, was deren Formtreue verbessert. die Wirksamkeit beider Konzepte bestätigen wir erfolgreich in experimentellen Prints. Die Verwendung optischer Metaoberflächen erweitert die Fähigkeiten zur Wellenfrontformung von Photomasken gegenüber etablierten Intensitäts- oder Phasenschiebermasken. Wir diskutieren zwei Designs für optische Metaoberflächen, die beide den vollen $2\,\pi$-Phasenbereich abdecken. Ein Design beinhaltet dabei noch einen plasmonischen Absorber, was zusätzliche Möglichkeiten bietet, den Transmissionskoeffizient anzupassen. Desweiteren beschreiben wir einen Algorithmus zur Berechnung des Maskenlayouts für beliebige Strukturen. Eine kontinuierliche Weiterentwicklung von Maskenjustierbelichtern ist unerlässlich, um Schritt zu halten mit der fortschreitenden Miniaturisierung in allen Bereich der Optik, der Mechanik und der Elektronik. Unsere Forschungsergebnisse ermöglichen es, die Auflösung der optischen Lithographie im Proximity-Modus zu verbessern und sich damit den zukünftigen Herausforderungen der optischen Industrie stellen zu können

Bayesian Analysis for Photolithographic Models

The use of optical proximity correction (OPC) as a resolution enhancement technique (RET) in microelectronic photolithographic manufacturing demands increasingly accurate models of the systems in use. Model building and inference techniques in the data science community have seen great strides in the past two decades in the field of Bayesian statistics. This work aims to demonstrate the predictive power of using Bayesian analysis as a method for parameter selection in lithographic models by probabilistically considering the uncertainty in physical model parameters and the wafer data used to calibrate them. We will consider the error between simulated and measured critical dimensions (CDs) as Student’s t-distributed random variables which will inform our likelihood function, via sums of log-probabilities, to maximize Bayes’ rule and generate posterior distributions for each parameter. Through the use of a Markov chain Monte Carlo (MCMC) algorithm, the model’s parameter space is explored to find the most credible parameter values. We use an affine invariant ensemble sampler (AIES) which instantiates many walkers which semi-independently explore the space in parallel, which lets us exploit the slow model evaluation time. Posterior predictive checks are used to analyze the quality of the models that use parameter values from their highest density intervals (HDIs). Finally, we explore the concept of model hierarchy, which is a flexible method of adding hyperparameters to the Bayesian model structure

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

Design Techniques for Lithography-Friendly Nanometer CMOS Integrated Circuits

The Integrated Circuits industry has been a major driver of the outstanding changes and improvements in the modern day technology and life style that we are observing in our day to day life. The continuous scaling of CMOS technology has been one of the major challenges and success stories. However, as the CMOS technology advances deeply into the deep sub-micron technology nodes, the whole industry (both manufacturing and design) is starting to face new challenges. One major challenge is the control of the variation in device parameters. Lithography variations result from the industry incapability to come up with new light sources with a smaller wavelength than ArF source (193 nm wavelength). In this research, we develop better understanding of the photo-lithography variations and their effect on how the design gets patterned. We investigate the state-of-the-art mask correction and design manipulation techniques. We are focusing in our study on the different Optical Proximity Correction (OPC) and design retargeting techniques to assess how we can improve both the functional and parametric yield. Our goal is to achieve a fast and accurate Model Based Re-Targeting (MBRT) technique that can achieve a better functional yield during manufacturing by establishing the techniques to produce more lithography-friendly targets. Moreover, it can be easily integrated into a fab's PDK (due to its relatively high speed) to feedback the exact final printing on wafer to the designers during the early design phase. In this thesis, we focus on two main topics. First is the development of a fast technique that can predict the final mask shape with reasonable accuracy. This is our proposed Model-based Initial Bias (MIB) methodology, in which we develop the full methodology for creating compact models that can predict the perturbation needed to get to an OPC initial condition that is much closer to the final solution. This is very useful in general in the OPC domain, where it can save almost 50% of the OPC runtime. We also use MIB in our proposed Model-Based Retargeting (MBRT) flow to accurately compute lithography hot-spots location and severity. Second, we develop the fast model-based retargeting methodology that is capable of fixing lithography hot spots and improving the functional yield. Moreover, in this methodology we introduce to the first time the concept of distributed retargeting. In distributed MBRT, not only the design portion that is suffering from the hot-spot is moving to get it fixed but also the surrounding designs and design fragments also contribute to the hot-spot fix. Our proposed model-based retargeting methodology also includes the multiple-patterning awareness as well as the electrical-connectivity-awareness (via-awareness). We used Mentor Graphics Calibre Litho-API c-based programing to develop all of the methodologies we explain in this thesis and tested it on 20nm and 10nm nodes

Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security

Today, electronic computing devices are critically involved in our daily lives, basic infrastructure, and national defense systems. With the growing number of threats against them, hardware-based security features offer the best chance for building secure and trustworthy cyber systems. In this dissertation, we investigate ways of making hardware-based security into a reality with primary focus on two areas: Hardware Trojan Detection and Physically Unclonable Functions (PUFs). Hardware Trojans are malicious modifications made to original IC designs or layouts that can jeopardize the integrity of hardware and software platforms. Since most modern systems critically depend on ICs, detection of hardware Trojans has garnered significant interest in academia, industry, as well as governmental agencies. The majority of existing detection schemes focus on test-time because of the limited hardware resources available at run-time. In this dissertation, we explore innovative run-time solutions that utilize on-chip thermal sensor measurements and fundamental estimation/detection theory to expose changes in IC power/thermal profile caused by Trojan activation. The proposed solutions are low overhead and also generalizable to many other sensing modalities and problem instances. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect Trojans quickly and with few false positives. Physically Unclonable Functions (PUFs) are circuits that rely on IC fabrication variations to generate unique signatures for various security applications such as IC authentication, anti-counterfeiting, cryptographic key generation, and tamper resistance. While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Yet, for several decades the Design-for-Manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Furthermore, since manufacturing variations are often harmful to IC yield, the existing DFM tools have been geared towards suppressing them (counter-intuitive for PUFs). In this dissertation, we make several improvements over current state-of-the-art work in PUFs. First, our approaches exploit existing DFM models to improve PUFs at physical layout and mask generation levels. Second, our proposed algorithms reverse the role of standard DFM tools and extend them towards improving PUF quality without harming non-PUF portions of the IC. Finally, since our approaches occur after design and before fabrication, they are applicable to all types of PUFs and have little overhead in terms of area, power, etc. The innovative and unconventional techniques presented in this dissertation should act as important building blocks for future work in cyber security