Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

Master of Science

thesisFully integrated, implantable, and wireless neural interface systems typically re-quire a forward data link in addition to the telemetry link that transmits data from the chip. One popular way to create this forward data link is to amplitude modulate the magnetic fi eld of the inductive link that provides the device with wireless power. However, the limitations of these channels when loaded with a recti fier and amplitude modulated have not previously been characterized, and this lack of understanding caused previous versions of the Integrated Neural Interface (INI) to have forward data communication issues, which needed to be corrected for the next generation of the device, INIR8. This thesis first develops an analytical method of characterizing this sort of wireless channel. It then shows measurement data that verifies the validity of the model in the desired region of operation. The available bandwidth as determined by this analytical method, and confirmed by simulation, is insufficient for many applications. Therefore, the next subject of this thesis is to increase the data rate beyond what the bandwidth of the system can intrinsically support by using an equalization technique. This technique is shown to support very robust data recovery under a variety of operating conditions and to data rates much higher than otherwise possible. Another way to improve the reliability of data recovery is to develop a robust digital control system with error detection capabilities. This was done for INIR8, and works very reliably. The end result of this eff ort is a very robust forward data communication in INIR8, as well as a new analytical method for characterizing inductively coupled channels with certain loads and modulation techniques

Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

High Temperature Electronics Design for Aero Engine Controls and Health Monitoring

There is a growing desire to install electronic power and control systems in high temperature harsh environments to improve the accuracy of critical measurements, reduce the amount of cabling and to eliminate cooling systems. Typical target applications include electronics for energy exploration, power generation and control systems. Technical topics presented in this book include:• High temperature electronics market• High temperature devices, materials and assembly processes• Design, manufacture and testing of multi-sensor data acquisition system for aero-engine control• Future applications for high temperature electronicsHigh Temperature Electronics Design for Aero Engine Controls and Health Monitoring contains details of state of the art design and manufacture of electronics targeted towards a high temperature aero-engine application. High Temperature Electronics Design for Aero Engine Controls and Health Monitoring is ideal for design, manufacturing and test personnel in the aerospace and other harsh environment industries as well as academic staff and master/research students in electronics engineering, materials science and aerospace engineering

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

High Temperature Electronics Design for Aero Engine Controls and Health Monitoring

There is a growing desire to install electronic power and control systems in high temperature harsh environments to improve the accuracy of critical measurements, reduce the amount of cabling and to eliminate cooling systems. Typical target applications include electronics for energy exploration, power generation and control systems. Technical topics presented in this book include:• High temperature electronics market• High temperature devices, materials and assembly processes• Design, manufacture and testing of multi-sensor data acquisition system for aero-engine control• Future applications for high temperature electronicsHigh Temperature Electronics Design for Aero Engine Controls and Health Monitoring contains details of state of the art design and manufacture of electronics targeted towards a high temperature aero-engine application. High Temperature Electronics Design for Aero Engine Controls and Health Monitoring is ideal for design, manufacturing and test personnel in the aerospace and other harsh environment industries as well as academic staff and master/research students in electronics engineering, materials science and aerospace engineering

Analog and Mixed Signal Design towards a Miniaturized Sleep Apnea Monitoring Device

Sleep apnea is a sleep-induced breathing disorder with symptoms of momentary and often repetitive cessations in breathing rhythm or sustained reductions in breathing amplitude. The phenomenon is known to occur with varying degrees of severity in literally millions of people around the world and cause a range of chronicle health issues. In spite of its high prevalence and serious consequences, nearly 80% of people with sleep apnea condition remain undiagnosed. The current standard diagnosis technique, termed polysomnography or PSG, requires the patient to schedule and undergo a complex full-night sleep study in a specially-equipped sleep lab. Due to both high cost and substantial inconvenience, millions of apnea patients are still undiagnosed and thus untreated. This research work aims at a simple, reliable, and miniaturized solution for in-home sleep apnea diagnosis purposes. The proposed solution bears high-level integration and minimal interference with sleeping patients, allowing them to monitor their apnea conditions at the comfort of their homes. Based on a MEMS sensor and an effective apnea detection algorithm, a low-cost single-channel apnea screening solution is proposed. A custom designed IC chip implements the apnea detection algorithm using time-domain signal processing techniques. The chip performs autonomous apnea detection and scoring based on the patient’s airflow signals detected by the MEMS sensor. Variable sensitivity is enabled to accommodate different breathing signal amplitudes. The IC chip was fabricated in standard 0.5-μm CMOS technology. A prototype device was designed and assembled including a MEMS sensor, the apnea detection IC chip, a PSoC platform, and wireless transceiver for data transmission. The prototype device demonstrates a valuable screening solution with great potential to reach the broader public with undiagnosed apnea conditions. In a battery-operated miniaturized medical device, an energy-efficient analog-to-digital converter is an integral part linking the analog world of biomedical signals and the digital domain with powerful signal processing capabilities. This dissertation includes the detailed design of a successive approximation register (SAR) ADC for ultra-low power applications. The ADC adopts an asynchronous 2b/step scheme that halves both conversion time and DAC/digital circuit’s switching activities to reduce static and dynamic energy consumption. A low-power sleep mode is engaged at the end of all conversion steps during each clock period. The technical contributions of this ADC design include an innovative 2b/step reference scheme based on a hybrid R-2R/C-3C DAC, an interpolation-assisted time-domain 2b comparison scheme, and a TDC with dual-edge-comparison mechanism. The prototype ADC was fabricated in 0.18μm CMOS process with an active area of 0.103 mm^(2), and achieves an ENoB of 9.2 bits and an FoM of 6.7 fJ/conversion-step at 100-kS/s