EXECUTION TIME – AREA TRADEOFF IN GAUSING RESIDUAL LOAD DECODER: INTEGRATED EXPLORATION OF CHAINING BASED SCHEDULE AND ALLOCATION IN HLS FOR HARDWARE ACCELERATORS

Design space exploration is an indispensable segment of High Level Synthesis (HLS) design of hardware accelerators. This paper presents a novel technique for Area-Execution time tradeoff using residual load decoding heuristics in genetic algorithms (GA) for integrated design space exploration (DSE) of scheduling and allocation. This approach is also able to resolve issues encountered during DSE of data paths for hardware accelerators, such as accuracy of the solution found, as well as the total exploration time during the process. The integrated solution found by the proposed approach satisfies the user specified constraints of hardware area and total execution time (not just latency), while at the same time offers a twofold unified solution of chaining based schedule and allocation. The cost function proposed in the genetic algorithm approach takes into account the functional units, multiplexers and demultiplexers needed during implementation. The proposed exploration system (ExpSys) was tested on a large number of benchmarks drawn from the literature for assessment of its efficiency. Results indicate an average improvement in Quality of Results (QoR) greater than 26 % when compared to a recent well known GA based exploration method

Automated course scheduler for Ashesi University College

Applied project submitted to the Department of Computer Science, Ashesi University College, in partial fulfillment of Bachelor of Science degree in Computer Science, April 2014Ashesi University College is faced with the challenge of effectively scheduling courses at the beginning of the semester so that there are no class clashes for both lecturers and students. In an attempt to solve the Course Timetabling Problem at Ashesi University College, five algorithms: Genetic Algorithm, Constraint Programing, Particle Swarm Optimization, Simulated Annealing and Tabu Search algorithm, which are known for their use in solving University Course Timetabling problems have been studied and based on their ease of implementation, their robustness in arriving at feasible solutions, their computational speed and whether an optimal solution is always guaranteed, Particle Swarm Optimization algorithm is chosen to implement a solution to the Ashesi University Course Timetabling problem. This project is focused on eliminating course conflicts and creating an optimal table based on teachers‟ preferences for certain timeslots to teach during the week. The paper outlines the assumptions and steps including explanations on Particle Swarm Optimization used in constructing the timetable base on teachers‟ preferences. Test conducted on the project proved that the use of Particle Swarm Optimization to solve the Ashesi Course Timetabling problems is in the right direction.Finally, the paper proposes a focus on other areas of the course timetabling problem at Ashesi University College, using the same Particle swarm optimization procedures described in the paper to help provide a complete solution to the timetabling problem of the school.Ashesi University Colleg

Escalonamento e alocação de registradores sob execução condicional

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós -Graduação em Computação.Esta dissertação descreve como resolver dois problemas clássicos da Síntese de Alto Nível, através de uma abordagem orientada à exploração de soluções alternativas. O primeiro é o problema de escalonamento de operações de um dado algoritmo sob restrição de recursos físicos, cuja solução define quando cada operação é executada, respeitando a ordem de precedência imposta pelo algoritmo. O segundo é a respectiva alocação de registradores, cuja solução determina quantos registradores são necessários no circuito digital para armazenar todos os valores produzidos por algumas operações até serem consumidos por outras. Como um algoritmo pode conter construções condicionais (ex. "if-then-else"), possivelmente aninhadas, o conceito de predicado é introduzido para permitir a modelagem de execução condicional, substituindo a tradicional noção de dependência de controle, que limita a exploração de paralelismo. Esta dissertação descreve a abordagem proposta, a modelagem que a ampara e a implementação de ferramentas que a suportam (escalonador e alocador). São apresentados resultados experimentais que se mostram promissores quando comparados aos obtidos em outras abordagens

High-Level Synthesis Scheduling and Allocation using Genetic Algorithms

In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to coverother architectural issues and (for example) providesways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods 1 Introduction High-level synthesis translates behavioral descriptions into digital network structures. During this translation the cycle steps in which operations start their execution must be determined (scheduling problem). A schedule induces a resource allocation (because some operations are execut..

High-Level Synthesis Scheduling and Allocation using Genetic Algorithms based on Constructive Topological Scheduling Techniques

In this article constructive scheduling methods combined with genetic algorithms are used to searchfor a suitable order to schedule the operations. The method is extended with an encoding capable of allocating supplementary resources during scheduling. This makes it very suitable in high-level synthesis strategies based on lower bound estimations techniques. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods 1 Introduction During high-level synthesis a behavioral description of a chip is translated into a digital network structure [McFa90]. The behavioral description consists of calculations (like additions, multiplications, logical operations etc.) and control structures (like conditionals, loops and procedure calls) which are used to transform input data into output data. The digital network structure consists of functional modules (adders, multipliers, ALUs, logical gates), storage (like r..

High-Level Synthesis Scheduling and Allocation using Genetic Algorithms based on Constructive Topological Scheduling Techniques

In this article constructive scheduling methods combined with genetic algorithms are used to searchfor a suitable order to schedule the operations. The method is extended with an encoding capable of allocating supplementary resources during scheduling. This makes it very suitable in high-level synthesis strategies based on lower bound estimations techniques. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods