Novel Single and Hybrid Finite Field Multipliers over GF(2m) for Emerging Cryptographic Systems

With the rapid development of economic and technical progress, designers and users of various kinds of ICs and emerging embedded systems like body-embedded chips and wearable devices are increasingly facing security issues. All of these demands from customers push the cryptographic systems to be faster, more efficient, more reliable and safer. On the other hand, multiplier over GF(2m) as the most important part of these emerging cryptographic systems, is expected to be high-throughput, low-complexity, and low-latency. Fortunately, very large scale integration (VLSI) digital signal processing techniques offer great facilities to design efficient multipliers over GF(2m). This dissertation focuses on designing novel VLSI implementation of high-throughput low-latency and low-complexity single and hybrid finite field multipliers over GF(2m) for emerging cryptographic systems. Low-latency (latency can be chosen without any restriction) high-speed pentanomial basis multipliers are presented. For the first time, the dissertation also develops three high-throughput digit-serial multipliers based on pentanomials. Then a novel realization of digit-level implementation of multipliers based on redundant basis is introduced. Finally, single and hybrid reordered normal basis bit-level and digit-level high-throughput multipliers are presented. To the authors knowledge, this is the first time ever reported on multipliers with multiple throughput rate choices. All the proposed designs are simple and modular, therefore suitable for VLSI implementation for various emerging cryptographic systems

Diseño de IP CORES de cifrado aplicado a telecomunicaciones

En la actualidad, se tiene un uso masivo de las telecomunicaciones y la información que se transmite es en su mayoría sensible. Existen desarrollos de elementos que hacen que dicha información sea ilegible a la vista de terceros no autorizados, sin embargo, no son reconfigurables y no es posible realizarle mejoras que eviten riesgos de privacidad. Este documento comprende el desarollo de un IP Core de cifrado AES-128/256 implementado en un Dispositivo Lógico Programable, que puede ser parte de un Sistema de Telecomunicaciones. El cifrador AES se conforma de un IP Core que cifra los datos y un IP Core que recupera los datos originales. Éstos IP Cores se desarrollaron de forma que sean reconfigurables por medio del software del sistema embebido en el que están contenidos, así como reutilizables en otros posibles sistemas digitales con otras aplicaciones debido a que cuentan con un protocolo estándar llamado AXI4-Stream que les permite comunicarse con otros sistemas que utilicen el mismo protocolo. Primero, se realizó un estudio del estado de la cuestión de los últimos cuatro años, profundizando particularmente en algoritmos de cifrado sobre FPGAs. Seguido de la comprensión de los conceptos que giran alrededor de un cifrador AES y el estudio de los diferentes elementos que son necesarios para la implementación hardware del mismo. AES cifra bloques de 128-bit cada vez, y utiliza una misma clave de 128/192/256-bit para cifrar y para descifrar, por lo que recibe el nombre de cifrador simétrico. Dicho cifrado consiste en un número de rondas que se aplican al bloque de datos de entrada, y en la última ronda el bloque de datos resultante es el dato cifrado o también conocido como criptograma. El diseño de la arquitectura hardware del estándar de cifrado AES, se describió y se simuló en Verilog tanto para el IP Core de Cifrado como para el IP Core de Descifrado. Además, les fue añadido un protocolo de comuncicación denominado AXI4-Stream que les permite comunicarse con cualquier módulo hardware que cuente con la misma interfaz. La implementación del sistema fue realizado utilizando la tarjeta de desarrollo Zedboard cuyo elemento principal es el Zynq . El desarrollo constó de dos elementos principales. El primero, una plataforma de hardware en la que se incluyen los dos IP Cores. Y el segundo, una plataforma de software capaz de controlar las entradas de datos al sistema, por medio de una hiper terminal. Con lo que se pudo verificar el cifrado AES-128 y descifrado AES-128 (ambos AXI4-Stream) de bloques de 128-bit de datos. La verificación del funcionamiento de los bloques hardware diseñados, fue contrastada con los vectores de prueba diseñados para este efecto por el Instituto Nacional de Estándares y Tecnología (NIST) [1]

Modeling and design for energy-efficient spintronic logic devices and circuits

The objective of the proposed research is the modeling and the design of energy-efficient and scalable novel spintronic devices. Over the past two decades, spintronic devices have achieved special status due to their advantages in terms of low-voltage operation, smaller footprint area, non-volatile memory, and compatibility with CMOS technology. To design efficient spin-based systems, researchers require the precise modeling of the physics of nanomagnets, piezoelectrics, thermal noise, and metallic nanowires. Using the models developed during the research, spintronic logic devices comprised of hybrid magnetic and piezoelectric structures are proposed. The delay, energy dissipation, and footprint area of the proposed devices are analyzed. Moreover, the proposed devices are used as building blocks to propose spin-based logic gates, pattern and image recognition circuits, long-range interconnects, interface circuits, and coupled-oscillators. The performance of the proposed circuits is benchmarked against CMOS and other spin-based circuits, which shows improved performance, especially in implementing non-Boolean applications and interface circuits.Ph.D

Heterogeneous Reconfigurable Fabrics for In-circuit Training and Evaluation of Neuromorphic Architectures

A heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over fabrics having LUTs constructed with either individual technology alone. Herein, a hierarchical top-down design approach is used to develop the HSCFPGA starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication paradigms. This facilitates a novel architectural approach to reduce leakage energy, minimize communication occurrence and energy cost by eliminating unnecessary data transfer, and support auto-tuning for resilience. Furthermore, HSC-FPGA enables new advantages of technology co-design which trades off alternative mappings between emerging devices and transistors at runtime by allowing dynamic remapping to adaptively leverage the intrinsic computing features of each device technology. HSC-FPGA offers a platform for fine-grained Logic-In-Memory architectures and runtime adaptive hardware. An orthogonal dimension of fabric heterogeneity is also non-determinism enabled by either low-voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Herein, consider the probabilistic spin logic p-bit device as a fabric element comprising a crossbar-structured weighted array. The Programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array\u27s weighted connections. Thus, the programmable weighted array forms a CLB-scale macro co-processing element with bitstream programmability. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n x m1 x m2 x ::: x mi weighted array as a configurable hardware circuit with an n-input layer followed by i ≥ 1 hidden layers. As neuromorphic architectures using post-CMOS devices increase in capability and network size, the utility and benefits of reconfigurable fabrics of neuromorphic modules can be anticipated to continue to accelerate