335 research outputs found
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links
Nowadays spike-based brain processing emulation is
taking off. Several EU and others worldwide projects are
demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or
NeuroGrid. The larger the brain process emulation on silicon is,
the higher the communication performance of the hosting
platforms has to be. Many times the bottleneck of these system
implementations is not on the performance inside a chip or a
board, but in the communication between boards. This paper
describes a novel modular Address-Event-Representation (AER)
FPGA-based (Spartan6) infrastructure PCB (the AER-Node
board) with 2.5Gbps LVDS high speed serial links over SATA
cables that offers a peak performance of 32-bit 62.5Meps (Mega
events per second) on board-to-board communications. The
board allows back compatibility with parallel AER devices
supporting up to x2 28-bit parallel data with asynchronous
handshake. These boards also allow modular expansion
functionality through several daughter boards. The paper is
focused on describing in detail the LVDS serial interface and
presenting its performance.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02/01Ministerio de Economía y Competitividad TEC2012-37868-C04-02/01Junta de Andalucía TIC-6091Ministerio de Economía y Competitividad PRI-PIMCHI-2011-076
LVDS Serial AER Link performance
Address-Event-Representation (AER) is a
communication protocol for transferring asynchronous events
between VLSI chips, originally developed for bio-inspired
processing systems (for example, image processing). Such
systems may consist of a complicated hierarchical structure
with many chips that transmit data among them in real time,
while performing some processing (for example, convolutions).
The event information is transferred using a high speed digital
parallel bus (typically 16 bits and 20ns-40ns per event). This
paper presents a testing platform for AER systems that allows
analysing a LVDS Serial AER link produced by a Spartan 3
FPGA, or by a commercial LVDS transceiver. The interface
allows up to 0.728 Gbps (~40Mev/s, 16 bits/ev). The eye
diagram ensures that the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0
SVITE: A Spike-Based VITE Neuro-Inspired Robot Controller
This paper presents an implementation of a neuro-inspired algorithm
called VITE (Vector Integration To End Point) in FPGA in the spikes domain.
VITE aims to generate a non-planned trajectory for reaching tasks in robots.
The algorithm has been adapted to work completely in the spike domain under
Simulink simulations. The FPGA implementation consists in 4 VITE in parallel
for controlling a 4-degree-of-freedom stereo-vision robot. This work represents
the main layer of a complex spike-based architecture for robot neuro-inspired
reaching tasks in FPGAs. It has been implemented in two Xilinx FPGA
families: Virtex-5 and Spartan-6. Resources consumption comparative between
both devices is presented. Results obtained for Spartan device could allow
controlling complex robotic structures with up to 96 degrees of freedom per
FPGA, providing, in parallel, high speed connectivity with other neuromorphic
systems sending movement references. An exponential and gamma distribution
test over the inter spike interval has been performed to proof the approach to the
neural code proposed.Ministerio de Economía y Competitividad TEC2012-37868-C04-0
A LVDS Serial AER Link
Address-Event-Representation (AER) is a
communication protocol for transferring asynchronous events
between VLSI chips, originally developed for bio-inspired
processing systems (for example, image processing). Such
systems may consist of a complicated hierarchical structure
with many chips that transmit data among them in real time,
while performing some processing (for example, convolutions).
The event information is transferred using a high speed digital
parallel bus (typically 16 bits and 20ns-40ns per event). This
paper presents a testing platform for AER systems that allows
to analyse a LVDS Serial AER link. The interface allows up to
0.7 Gbps (~40Mev/s, 16 bits/ev). The eye diagram ensures that
the platform could support 1.2 Gbps.Commission of the European Communities IST-2001-34124 (CAVIAR)Comisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-0
A FPGA Spike-Based Robot Controlled with Neuro-inspired VITE
This paper presents a spike-based control system applied to a fixed
robotic platform. Our aim is to take a step forward to a future complete spikes
processing architecture, from vision to direct motor actuation. This paper covers
the processing and actuation layer over an anthropomorphic robot. In this way,
the processing layer uses the neuro-inspired VITE algorithm, for reaching a target,
based on PFM taking advantage of spike system information: its frequency.
Thus, all the blocks of the system are based on spikes. Each layer is implemented
within a FPGA board and spikes communication is codified under the
AER protocol. The results show an accurate behavior of the robotic platform
with 6-bit resolution for a 130º range per joint, and an automatic speed control
of the algorithm. Up to 96 motor controllers could be integrated in the same
FPGA, allowing the positioning and object grasping by more complex anthropomorphic
robots.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Economía y Competitividad TEC2012-37868-C04-0
Event-based control system on FPGA applied to the pencil balancer robotic platform
An event-based motor controller design is presented.
The system is designed to solve the classic inverted
pendulum problem by using a robotic platform and a totally
neuro-inspired event-based mechanism. Specifically, DVS retinas
provide feedback and an FPGA implements control. The robotic
platform used is the so called ’pencil balancer’. The retinas
provide visual information to the FPGA that processes it and
obtains the center of mass of the pencil. Once this center of
mass is averaged over time, it is used joint with the cart position
provided by a flat potentiometer bar to compute the angle of
the pencil from the vertical. The angle is delivered to an eventbased
Proportional-Derivative (PD) controller that drives the DC
motor using Pulse Frequency Modulation (PFM) to accomplish
the control objective. The results show an accurate, real-time and
efficient controller design
Retinal ganglion cell software and FPGA model implementation for object detection and tracking
This paper describes the software and FPGA
implementation of a Retinal Ganglion Cell model which detects
moving objects. It is shown how this processing, in conjunction
with a Dynamic Vision Sensor as its input, can be used to
extrapolate information about object position. Software-wise, a
system based on an array of these of RGCs has been developed in
order to obtain up to two trackers. These can track objects in a
scene, from a still observer, and get inhibited when saccadic
camera motion happens. The entire processing takes on average
1000 ns/event. A simplified version of this mechanism, with a mean
latency of 330 ns/event, at 50 MHz, has also been implemented in
a Spartan6 FPGA.European Commission FP7-ICT-600954Ministerio de Economía y Competitividad TEC2012-37868-C04-02Junta de Andalucía P12-TIC-130
Live Demonstration: Retinal ganglion cell software and FPGA implementation for object detection and tracking
This demonstration shows how object detection and
tracking are possible thanks to a new implementation which
takes inspiration from the visual processing of a particular type
of ganglion cell in the retina
Address-Event based Platform for Bio-inspired Spiking Systems
Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate "events" according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems, it is absolutely necessary to have a computer interface that allows (a) reading AER interchip traffic into the computer and visualizing it on the screen, and (b) converting conventional frame-based video stream in the computer into AER and injecting it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. In the other hand, the use of a commercial personal computer implies to depend on software tools and operating systems that can make the system slower and un-robust. This paper addresses the problem of communicating several AER based chips to compose a powerful processing system. The problem was discussed in the Neuromorphic Engineering Workshop of 2006. The platform is based basically on an embedded computer, a powerful FPGA and serial links, to make the system faster and be stand alone (independent from a PC). A new platform is presented that allow to connect up to eight AER based chips to a Spartan 3 4000 FPGA. The FPGA is responsible of the network communication based in Address-Event and, at the same time, to map and transform the address space of the traffic to implement a pre-processing. A MMU microprocessor (Intel XScale 400MHz Gumstix Connex computer) is also connected to the FPGA to allow the platform to implement eventbased algorithms to interact to the AER system, like control algorithms, network connectivity, USB support, etc. The LVDS transceiver allows a bandwidth of up to 1.32 Gbps, around ~66 Mega events per second (Mevps)
Neuro-inspired system for real-time vision sensor tilt correction
Neuromorphic engineering tries to mimic biological
information processing. Address-Event-Representation (AER)
is an asynchronous protocol for transferring the information of
spiking neuro-inspired systems. Currently AER systems are able
sense visual and auditory stimulus, to process information, to
learn, to control robots, etc. In this paper we present an AER
based layer able to correct in real time the tilt of an AER vision
sensor, using a high speed algorithmic mapping layer. A codesign
platform (the AER-Robot platform), with a Xilinx
Spartan 3 FPGA and an 8051 USB microcontroller, has been
used to implement the system. Testing it with the help of the
USBAERmini2 board and the jAER software.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-02Ministerio de Ciencia e Innovación TEC2009-10639-C04-0
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