Device Modeling and Circuit Design of Neuromorphic Memory Structures

The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided

Resistive switching RAM devices based on amorphous oxide semiconductors for system on panel applications

This work reports the mask design, fabrication and characterization of memristor devices with diode like electrical behavior at pristine state. It is due to the presence of Schottky junctions between Zinc-tin-oxide (ZTO) and platinum - Indium-galliumzinc- oxide (IGZO) and molybdenum oxide for two different Metal-Insulator-Metal (MIM) configurations. The devices were exclusively produced using physical vapor deposition processes without intentional heating. Typical advanced electrical analysis of ReRAM device was performed. The Pt-ZTO-TiAu devices showed pinched hysteresis properties with large Ron=of f ratio, fast switching which can be controlled in a digital SET and analog RESET operation. However, large device-to-device variations and stability are the main issues which is due to the processing. On the other hand, the Mo-IGZO-Mo devices showed a small Ron=of f ratio and only analog operation. There was a high yield and stability. However, using DC sweep for cycling led to a charging phenomenon. Using SET/RESET pulses, the devices sustain hundreds of cycles without deterioration or movement of the resistance states, showing great resilience and retention

A Complementary Resistive Switch-based Crossbar Array Adder

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic sneak currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.Comment: 12 pages, accepted for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), issue on Computing in Emerging Technologie

Improving Performance and Endurance for Crossbar Resistive Memory

Resistive Memory (ReRAM) has emerged as a promising non-volatile memory technology that may replace a significant portion of DRAM in future computer systems. When adopting crossbar architecture, ReRAM cell can achieve the smallest theoretical size in fabrication, ideally for constructing dense memory with large capacity. However, crossbar cell structure suffers from severe performance and endurance degradations, which come from large voltage drops on long wires. In this dissertation, I first study the correlation between the ReRAM cell switching latency and the number of cells in low resistant state (LRS) along bitlines, and propose to dynamically speed up write operations based on bitline data patterns. By leveraging the intrinsic in-memory processing capability of ReRAM crossbars, a low overhead runtime profiler that effectively tracks the data patterns in different bitlines is proposed. To achieve further write latency reduction, data compression and row address dependent memory data layout are employed to reduce the numbers of LRS cells on bitlines. Moreover, two optimization techniques are presented to mitigate energy overhead brought by bitline data patterns tracking. Second, I propose XWL, a novel table-based wear leveling scheme for ReRAM crossbars and study the correlation between write endurance and voltage stress in ReRAM crossbars. By estimating and tracking the effective write stress to different rows at runtime, XWL chooses the ones that are stressed the most to mitigate. Additionally, two extended scenarios are further examined for the performance and endurance issues in neural network accelerators as well as 3D vertical ReRAM (3D-VRAM) arrays. For the ReRAM crossbar-based accelerators, by exploiting the wearing out mechanism of ReRAM cell, a novel comprehensive framework, ReNEW, is proposed to enhance the lifetime of the ReRAM crossbar-based accelerators, particularly for neural network training. To reduce the write latency in 3D-VRAM arrays, a collection of techniques, including an in-memory data encoding scheme, a data pattern estimator for assessing cell resistance distributions, and a write time reduction scheme that opportunistically reduces RESET latency with runtime data patterns, are devised

Resistive Switching in Transition Metal Oxides for Integrated Non-volatile Memory

Transition metal oxides (TMOs) exhibit characteristic resistance changes when subjected to high electric fields due to the creation, drift and diffusion of defects, and this resistive-switching response is of interest for future non-volatile memory applications. Indeed, resistive random access memories (ReRAM) are considered promising alternatives to conventional charge storage-based devices because of their low production cost, simple fabrication, and excellent scalability. However, the realization of reliable ReRAM devices and their integration in large-scale arrays requires further understanding of the switching mechanisms and the development of new strategies for improving integrated device functionality. The aim of this work is to understand the role of the material structure on device reliability and to investigate the integration of passive selector elements with memory devices for use in memory cross-bar arrays. The thesis begins by investigating the properties of relevant oxide films (ALD HfO2 and plasma deposited NbOx) and then addresses three technologically relevant problems. Specifically these include: 1) understanding how the roughness of metal/dielectric interfaces affects dielectric breakdown and switching behaviour; 2) exploring methods for reducing the operating current of selector and memory/selector devices and 3) investigating the effect of operating conditions on the switching response of devices. The first of these studies is based on Pt/Ti/HfO2/Pt devices and combines experimental methods and finite element modelling to understand the effect of the Pt/HfO2 interface roughness on the electroforming and switching response. Atomic force microscopy (AFM) showed that the roughness of Pt electrodes deposited by electron-beam evaporation increased with film thickness due to facetted grain growth. Results show that roughness leads to a reduction in the electroforming voltage of HfO2, an increase in the failure rate of devices, and a corresponding reduction in resistive switching reliability. Conventional wisdom suggests that these effects result from local electric field enhancement in the vicinity of electrode asperities. However, the effect on electroforming voltage is much less than estimated from simple geometric considerations. Comparison with finite-element modelled showed high-aspect-ratio asperities can produce field enhancements of more than an order of magnitude but that the generation and redistribution of defects moderates this effect prior to dielectric breakdown. As a consequence, the effect of field enhancement is less than anticipated from the initial electric-field distribution alone. It is argued that the increase in the device failure rate with increasing electrode roughness derives partly from an increase in the film defect density and effective device area and that these effects contribute to the reduction in breakdown voltage. The second study showed that the leakage current in NbO2-x selector (1S) elements is shown to be reduced by the properties of an adjacent memory (1M) element when integrated into a hybrid selector-memory device structure. This is shown to result from current confinement in conductive filaments formed in the memory layer. Finite element modelling of the selector-memory structures is used to confirm the observations and to explore material dependencies. The thermal and electrical conductivities of the memory layer are shown to influence the threshold current, but the dominant effect is due to current confinement. The final study explores the effect of device operating conditions on its operation and identifies an alternative approach for reducing the forming and RESET current in integrated memory/selector devices. This study is based on Pt/Nb/HfO2/Pt devices which require a very "soft" electroforming process. Such devices are shown to undergo configurable switching controlled by the SET compliance current. When operated at a low compliance-current (~100 µA), devices show uniform bipolar resistive switching behaviour. As the compliance current is increased (~500 µA), the switching mode changes to integrated threshold-resistive (1S1M) switching, and at still higher currents (~1 mA), it changes to symmetric threshold switching (1S) characteristic of threshold switching in NbO2-. These switching transitions are shown to be consistent with the development of an NbO2- interlayer at the Nb/HfO2 interface that is limited by the set compliance current due to its effect on oxygen transport and local Joule heating. The proposed mechanism is supported by finite element modelling of the 1S1M response assuming the presence of such an interlayer. These findings help to understand role of interface reactions in controlling device performance and provide a means for the self-assembly of integrated 1S1M resistive random access memory structures

Fabrication, Characterization and Integration of Resistive Random Access Memories

The functionalities and performances of today's computing systems are increasingly dependent on the memory block. This phenomenon, also referred as the Von Neumann bottleneck, is the main motivation for the research on memory technologies. Despite CMOS technology has been improved in the last 50 years by continually increasing the device density, today's mainstream memories, such as SRAM, DRAM and Flash, are facing fundamental limitations to continue this trend. These memory technologies, based on charge storage mechanisms, are suffering from the easy loss of the stored state for devices scaled below 10 nm. This results in a degradation of the performance, reliability and noise margin. The main motivation for the development of emerging non volatile memories is the study of a different mechanism to store the digital state in order to overcome this challenge. Among these emerging technologies, one of the strongest candidate is Resistive Random Access Memory (ReRAM), which relies on the formation or rupture of a conductive filament inside a dielectric layer. This thesis focuses on the fabrication, characterization and integration of ReRAM devices. The main subject is the qualitative and quantitative description of the main factors that influence the resistive memory electrical behavior. Such factors can be related either to the memory fabrication or to the test environment. The first category includes variations in the fabrication process steps, in the device geometry or composition. We discuss the effect of each variation, and we use the obtained database to gather insights on the ReRAM working mechanism and the adopted methodology by using statistical methods. The second category describes how differences in the electrical stimuli sent to the device change the memory performances. We show how these factors can influence the memory resistance states, and we propose an empirical model to describe such changes. We also discuss how it is possible to control the resistance states by modulating the number of input pulses applied to the device. In the second part of this work, we present the integration of the fabricated devices in a CMOS technology environment. We discuss a Verilog-A model used to simulate the device characteristics, and we show two solutions to limit the sneak-path currents for ReRAM crossbars: a dedicated read circuit and the development of selector devices. We describe the selector fabrication, as well as the electrical characterization and the combination with our ReRAMs in a 1S1R configuration. Finally, we show two methods to integrate ReRAM devices in the BEoL of CMOS chips

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing