High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm