Discussion of the technology and research in fuel injectors common rail system

Common rail is one of the most important components in a diesel and gasoline direct injection system. It features a high-pressure (100 bar) fuel rail feeding solenoid valves, as opposed to a low-pressure fuel pump feeding unit injectors. Third-generation common rail diesels now feature piezoelectric injectors for increased precision, with fuel pressures up to 2,500 bar. The purpose of this review paper is to investigate the technology and research in fuel injectors common rail system. This review paper focuses on component of common rail injection system, pioneer of common rail injection, characteristics of common rail injection system, method to reduce smoke and NOx emission simultaneously and impact of common rail injection system. Based on our research, it can be concluded that common rail injection gives many benefit such as good for the engine performance, safe to use, and for to reduce the emission of the vehicle. Fuel injection common rail system is the modern technology that must be developed. Nowadays, our earth is polluting by vehicle output such as smoke. If the common rail system is developed, it can reduce the pollution and keep our atmosphere clean and safe

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.Comment: 15 pages, contribution to the 2014 CAS - CERN Accelerator School: Power Converters, Baden, Switzerland, 7-14 May 201

Back-to-back Converter Control of Grid-connected Wind Turbine to Mitigate Voltage Drop Caused by Faults

Power electronic converters enable wind turbines, operating at variable speed, to generate electricity more efficiently. Among variable speed operating turbine generators, permanent magnetic synchronous generator (PMSG) has got more attentions due to low cost and maintenance requirements. In addition, the converter in a wind turbine with PMSG decouples the turbine from the power grid, which favors them for grid codes. In this paper, the performance of back-to-back (B2B) converter control of a wind turbine system with PMSG is investigated on a faulty grid. The switching strategy of the grid side converter is designed to improve voltage drop caused by the fault in the grid while the maximum available active power of wind turbine system is injected to the grid and the DC link voltage in the converter is regulated. The methodology of the converter control is elaborated in details and its performance on a sample faulty grid is assessed through simulation

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

Investigation of the Coupling Paths of a Galvanically Isolated AC/AC Converter

A galvanically isolated three-phase AC/AC converter with a high-frequency AC-link has been analyzed from an EMC point of view. This is a special configuration because of a large number of switches, a high frequency transformer, and a fourwire output. The essential coupling paths are identified.\ud Corresponding suppression remedies are given. The results, before and after measures, have been presented to demonstrate the improvement in EMC.\ud Keywords: AC/AC converter; electromagnetic interference; galvanically isolated\u

Full- & Reduced-Order State-Space Modeling of Wind Turbine Systems with Permanent-Magnet Synchronous Generator

Wind energy is an integral part of nowadays energy supply and one of the fastest growing sources of electricity in the world today. Accurate models for wind energy conversion systems (WECSs) are of key interest for the analysis and control design of present and future energy systems. Existing control-oriented WECSs models are subject to unstructured simplifications, which have not been discussed in literature so far. Thus, this technical note presents are thorough derivation of a physical state-space model for permanent magnet synchronous generator WECSs. The physical model considers all dynamic effects that significantly influence the system's power output, including the switching of the power electronics. Alternatively, the model is formulated in the $(a,b,c)$- and $(d,q)$-reference frame. Secondly, a complete control and operation management system for the wind regimes II and III and the transition between the regimes is presented. The control takes practical effects such as input saturation and integral windup into account. Thirdly, by a structured model reduction procedure, two state-space models of WECS with reduced complexity are derived: a non-switching model and a non-switching reduced-order model. The validity of the models is illustrated and compared through a numerical simulation study.Comment: 23 pages, 11 figure

Image-based oil palm leaf disease detection using convolutional neural network

Over the years, numerous studies have been conducted on the integration of computer vision and machine learning in plant disease detection. However, these conventional machine learning methods often require the contour segmentation of the infected region from the entire leaf region and the manual extraction of different discriminative features before the classification models can be developed. In this study, deep learning models, specifically, the AlexNet convolutional neural network (CNN) and the combination of AlexNet and support vector machine (AlexNet-SVM), which overcome the limitation of handcrafting of feature representation were implemented for oil palm leaf disease identification. The images of healthy and infected leaf samples were collected, resized, and renamed before the model training. These images were directly used to fit the classification models, without the need for segmentation and feature extraction as in the conventional machine learning methods. The optimal architecture of AlexNet CNN and AlexNet-SVM models were then determined and subsequently applied for the oil palm leaf disease identification. Comparative studies showed that the overall performance of the AlexNet CNN model outperformed AlexNet-SVM-based classifier

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m