A handheld high-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays

We report a micro-nuclear magnetic resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale (dimension: 14 x 6 x 11 cm³, weight: 1.4 kg), the system is capable to detect<100 pM of Enterococcus faecalis derived DNA from a 2.5 μL sample. The key components are a portable magnet (0.46 T, 1.25 kg) for nucleus magnetization, a system PCB for I/O interface, an FPGA for system control, a current driver for trimming the magnetic (B) field, and a silicon chip fabricated in 0.18 μm CMOS. The latter, integrated with a current-mode vertical Hall sensor and a low-noise readout circuit, facilitates closed-loop B-field stabilization (2 mT → 0.15 mT), which otherwise fluctuates with temperature or sample displacement. Together with a dynamic-B-field transceiver with a planar coil for micro-NMR assay and thermal control, the system demonstrates: 1) selective biological target pinpointing; 2) protein state analysis; and 3) solvent-polymer dynamics, suitable for healthcare, food and colloidal applications, respectively. Compared to a commercial NMR-assay product (Bruker mq-20), this platform greatly reduces the sample consumption (120x), hardware volume (175x), and weight (96x)

Remediation of contaminated marine sediment using bentonite, kaolin and sand as capping materials

There is a growing public concern over the issue of sediment contamination resulting from industrial, municipal wastewater, mining activities, and improper use of chemical fertilizer or pesticides. The conventional treatment of contaminated sediment is dredging, but this treatment is expensive and requires a large area of land for disposal. In situ capping of contaminated sediment is considered as a cheaper technique compared to dredging and efficient treatment technology to immobilize pollutants in sediments on site. In this technique, sediments are capped by placing a layer of inert materials like sand, clean soil, or gravel or active materials like activated carbon, zeolite, or apatite over sediments in order to reduce the risk to the aquatic environment. The objective of this study is to determine the effectiveness of using active materials; bentonite (B), kaolin (K), mixture of bentonite with kaolin (1:1) (BK) as capping materials to block the release of five heavy metals (Pb, Cr, Cu, Cd and Zn) from artificially polluted sediments. The effectiveness of B, K, and BK for preventing the leachability of the trace metals was assessed on a bench-scale laboratory experiment in glass tanks for 90 days, where 1cm thick layer of capping material and sand was placed above the contaminated sediment. The results showed that B and BK reduced the leachability of Pb, Cr, and Cu from the sediments. The results also showed that B and BK could be used as potential capping materials for the remediation of contaminated sites due to their significant entrapping of Pb, Cu, and Cr. The pollutants were released into the overlying water from the contaminated sediment in the following decreasing order; Cd > Zn > Pb > Cu > Cr. The adsorption kinetics analysis also showed that the process of adsorption was by chemisorption. This study proved that bentonite and mixture of bentonite with kaolin clays covered with sand could be used as capping materials for in situ treatment of Pb, Cu, Cr, Zn, and Cd for contaminated marine sediment

Device modelling for bendable piezoelectric FET-based touch sensing system

Flexible electronics is rapidly evolving towards devices and circuits to enable numerous new applications. The high-performance, in terms of response speed, uniformity and reliability, remains a sticking point. The potential solutions for high-performance related challenges bring us back to the timetested silicon based electronics. However, the changes in the response of silicon based devices due to bending related stresses is a concern, especially because there are no suitable models to predict this behavior. This also makes the circuit design a difficult task. This paper reports advances in this direction, through our research on bendable Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) based touch sensors. The analytical model of POSFET, complimented with Verilog-A model, is presented to describe the device behavior under normal force in planar and stressed conditions. Further, dynamic readout circuit compensation of POSFET devices have been analyzed and compared with similar arrangement to reduce the piezoresistive effect under tensile and compressive stresses. This approach introduces a first step towards the systematic modeling of stress induced changes in device response. This systematic study will help realize high-performance bendable microsystems with integrated sensors and readout circuitry on ultra-thin chips (UTCs) needed in various applications, in particular, the electronic skin (e-skin)

Reconfigurable nanoelectronics using graphene based spintronic logic gates

This paper presents a novel design concept for spintronic nanoelectronics that emphasizes a seamless integration of spin-based memory and logic circuits. The building blocks are magneto-logic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and present a spin-based circuit design with smaller area, faster speed, and lower energy consumption than the state-of-the-art CMOS counterparts. This design can also be applied in applications such as data compression, coding and image recognition. In the proposed scheme, over 100 spin-based logic operations are carried out before any need for a spin-charge conversion. Consequently, supporting CMOS electronics requires little power consumption. The spintronic-CMOS integrated system can be implemented on a single 3-D chip. These nonvolatile logic circuits hold potential for a paradigm shift in computing applications.Comment: 14 pages (single column), 6 figure

Three-dimensional magnetic field sensor in IBM 0.18μm CMOS technology

This work presents a compact three-dimensional Magnetic Field Sensor (MFS) designed in standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. A circular Vertical Hall Device (VHD) for horizontal magnetic field detection and a split- drain Horizontal Hall Device (HHD) for the vertical magnetic field detection are integrated to implement the three-dimensional M FS. This merged design has the advantage of smaller area and lower power consumption. The sensitivity of the vertical hall device (ring-shaped magneto-resistor) and the horizontal hall device (Split-Drain Magnetic Field-Effect Transistor (SD-MAGFET)) is estimated as 0.11V/T and 2.88V/T respectively. The vertical direction of the magnetic field detection demonstrates a higher sensitivity. A high gain cascode differential amplifier is integrated with the sensor to further amplify the magnetic signal

Hall probes: physics and application to magnetometry

This lecture aims to present an overview of the properties of Hall effect devices. Descriptions of the Hall phenomenon, a review of the Hall effect device characteristics and of the various types of probes are presented. Particular attention is paid to the recent development of three-axis sensors and the related techniques to cancel the offsets and the planar Hall effect. The lecture introduces the delicate problem of the calibration of a three-dimensional sensor and ends with a section devoted to magnetic measurements in conventional beam line magnets and undulators.Comment: 40 pages, presented at the CERN Accelerator School CAS 2009: Specialised Course on Magnets, Bruges, 16-25 June 200

SOT-MRAM 300mm integration for low power and ultrafast embedded memories

We demonstrate for the first time full-scale integration of top-pinned perpendicular MTJ on 300 mm wafer using CMOS-compatible processes for spin-orbit torque (SOT)-MRAM architectures. We show that 62 nm devices with a W-based SOT underlayer have very large endurance (> 5x10^10), sub-ns switching time of 210 ps, and operate with power as low as 300 pJ.Comment: presented at VLSI2018 session C8-

ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3×3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.LOCUST IST2001—38 097VISTA TIC2003—09 817 - C02—01Office of Naval Research N000 140 210 88