Advanced analog layout design automation in compliance with density uniformity

To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control

トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.北九州市立大

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Metal fill considerations for on-chip interconnects and spiral inductors

Variability in circuit performance due to process defects is a major concern in integrated circuit (IC) fabrication. Advanced IC manufacturing processes employ Chemical-Mechanical Polishing (CMP) for planarization of oxide and metal layers. CMP defects result in variations in the oxide and metal topographical profile. To reduce these topographical variations, electrically non-functional (dummy) metal features are added in low metal density regions. These metal fills degrade the performance of on-chip interconnects and components, and the overall circuit due to the additional electrical parasitics. Therefore, it is important to characterize the parasitic effects of metal fill on critical structures such as interconnects and spiral inductors. This thesis presents a study of the impact of metal fill placement, size, and shape on the electrical performance of representative on-chip transmission line structures and spiral inductors. We separate the electric and magnetic effects of different metal fill designs by studying their impact on parasitic capacitance and eddy-current loss. The study is done through simulation using a commercial full-wave electromagnetic simulator and measurement of a test chip fabricated in a 180nm BiCMOS process, and is supported through theoretical considerations. For a reduction in fill size of about 90% while keeping the same metal density, we find a significant reduction in parasitic microstrip capacitance and microstrip resistance by about 30% compared to the larger fill size. Similarly, a 70% decrease in fill size provides an improvement of about 13% in measured quality factor of a representative spiral inductor design. Using octagonal metal fill shapes reduces the parasitic microstrip capacitance by about 45% and microstrip resistance by about 13% compared to square shapes with the same metal density. Furthermore, measurement results for a spiral inductor show larger impact on the quality factor and self-resonance frequency for off-plane metal fill compared to in-plane metal fill

EDA Solutions for Double Patterning Lithography

Expanding the optical lithography to 32-nm node and beyond is impossible using existing single exposure systems. As such, double patterning lithography (DPL) is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Among different DPL techniques litho-etch-litho-etch (LELE) and self-aligned double patterning (SADP) methods are the most popular ones, which apply two complete exposure lithography steps and an exposure lithography followed by a chemical imaging process, respectively. To realize double patterning lithography, patterns located within a sub-resolution distance should be assigned to either of the imaging sub-processes, so-called layout decomposition. To achieve the optimal design yield, layout decomposition problem should be solved with respect to characteristics and limitations of the applied DPL method. For example, although patterns can be split between the two sub-masks in the LELE method to generate conflict free masks, this pattern split is not favorable due to its sensitivity to lithography imperfections such as the overlay error. On the other hand, pattern split is forbidden in SADP method because it results in non-resolvable gap failures in the final image. In addition to the functional yield, layout decomposition affects parametric yield of the designs printed by double patterning. To deal with both functional and parametric challenges of DPL in dense and large layouts, EDA solutions for DPL are addressed in this thesis. To this end, we proposed a statistical method to determine the interconnect width and space for the LELE method under the effect of random overlay error. In addition to yield maximization and achieving near-optimal trade-off between different parametric requirements, the proposed method provides valuable insight about the trend of parametric and functional yields in future technology nodes. Next, we focused on self-aligned double patterning and proposed layout design and decomposition methods to provide SADP-compatible layouts and litho-friendly decomposed layouts. Precisely, a grid-based ILP formulation of SADP decomposition was proposed to avoid decomposition conflicts and improve overall printability of layout patterns. To overcome the limited applicability of this ILP-based method to fully-decomposable layouts, a partitioning-based method is also proposed which is faster than the grid-based ILP decomposition method too. Moreover, an A∗-based SADP-aware detailed routing method was proposed which performs detailed routing and layout decomposition simultaneously to avoid litho-limited layout configurations. The proposed router preserves the uniformity of pattern density between the two sub-masks of the SADP process. We finally extended our decomposition method for double patterning to triple patterning and formulated SATP decomposition by integer linear programming. In addition to conventional minimum width and spacing constraints, the proposed decomposition method minimizes the mandrel-trim co-defined edges and maximizes the layout features printed by structural spacers to achieve the minimum pattern distortion. This thesis is one of the very early researches that investigates the concept of litho-friendliness in SADP-aware layout design and decomposition. Provided by experimental results, the proposed methods advance prior state-of-the-art algorithms in various aspects. Precisely, the suggested SADP decomposition methods improve total length of sensitive trim edges, total EPE and overall printability of attempted designs. Additionally, our SADP-detailed routing method provides SADP-decomposable layouts in which trim patterns are highly robust to lithography imperfections. The experimental results for SATP decomposition show that total length of overlay-sensitive layout patterns, total EPE and overall printability of the attempted designs are also improved considerably by the proposed decomposition method. Additionally, the methods in this PhD thesis reveal several insights for the upcoming technology nodes which can be considered for improving the manufacturability of these nodes

Silicon nitride Arrayed Waveguide Gratings

Le développement des télécommunications optiques à haute capacité fait des multiplexeurs en longueur d'onde un sujet brûlant des récentes recherches. Dans cette thèse, nous proposons et démontrons des réseaux sélectifs planaires ou (Arrayed Waveguide Grating, AWG) basés sur une plateforme de Nitrure de silicium (SiN) comme multiplexeur ou démultiplexeur. Dans le premier chapitre, nous comparons les guides d'onde en silicium et en nitrure de silicium et confirmons que le SiN sera considéré comme la plateforme principale de ce travail. Nous présentons des simulations des guides d'onde de SiN qui forme les AWGs, incluant les guides d'onde planaires, les guides d'onde à bande, les guides d'onde courbés et les guides d'onde fuselée utilisant FDTD solution et Mode solution d'Ansys Lumerical. L'influence des paramètres de conceptions des AWGs en SiN tels que la longueur focale, la distance séparant les guides d'onde, l'espacement entre les ouvertures adjacentes et les pertes de propagation liées à la fabrication sur les performances est aussi étudié en utilisant sur un modèle semi-analytique. Les AWGs communs sont typiquement conçus pour les modes électriques transverses (TE). Pour améliorer la capacité de transmission des réseaux WDM, dans le second chapitre, nous présentons un AWG insensible à la polarisation conçus avec des guides d'onde en SiN. L'insensibilité à la polarisation des AWGs est obtenue lorsque l'espace intercanal et la longueur d'onde centrale des deux modes sont alignés pour un même AWG. L'alignement de l'espace intercanal entre les deux états de polarisations est obtenu en optimisant la géométrie du réseau de guide d'onde, alors que l'insensibilité de la longueur d'onde centrale est obtenue en séparant les deux états de polarisations et en ajustant leur angle d'incidence à l'entrée du coupleur en étoile pour compenser la dispersion entre les modes dans l'AWG. Un multiplexeur de longueur d'onde 1 × 8 avec un espacement entre les canaux de 100 GHz et une diaphonie de −16 dB est démontré expérimentalement. Dans la conception d'un AWGs en SiN, un espacement d'une largeur supérieur à 10 µm entre des guides d'ondes identiques minimise le couplage parasite augmentant ainsi leur empreinte. Dans le troisième chapitre, nous présentons un AWG ultra-compact 1×8 ayant une séparation de 100 GHz entre les canax rendu possible grâce à des guides d'onde en super-réseaux supprimant le couplage entre les guides d'onde. Bénéficiant de la haute densité du super-réseau, cet AWG possède une empreinte compacte de 4.3mm × 0.6mm, ce qui est plus que 2 fois plus petit qu'un AWG conventionnel ayant des performances similaires à celui présenté dans le second chapitre. Le SL-AWG montre aussi une faible perte d'insertion de 3.4 dB et une faible diaphonie de −18 dB. À part le couplage entre les guides d'onde discuté dans le troisième chapitre, l'erreur de phase produite par les variations de fabrication a l'impact le plus important sur les performances de l'AWG. Il a été étudié que leurs performances sont liées à la longueur du réseau de guide d'onde déterminant l'erreur de phase. Toutefois, il existe encore un écart de quantification de l'impact de la longueur du réseau et les variations de fabrication sur les performances de l'AWG. Dans le quatrième chapitre, nous présentons une analyse statistique de l'AWG en présence d'erreurs de phase dans les guides d'onde. Des figures de mérites importantes pour la performance incluant les pertes d'insertion, la diaphonie et la non-uniformité sont paramétrées en fonction de la longueur de cohérence, un paramètre physique qui caractérise l'accumulation d'erreur de phase dans les guides d'ondes optique. Une longueur de cohérence de 23.7 mm au niveau de la matrice pour les guides d'onde de SiN peut être extraite en mesurant les variations dans la longueur d'onde de résonnance d'un interféromètre de Mach-Zhender. Au travers de simulations Monte-Carlo, nous examinons l'impact de l'erreur de phase sur les performances de l'AWG avec une espace entre les canaux de 100 GHz et 200 GHz.The development of optical communications with high transmission capacity makes wavelength division multiplexing (WDM) systems a hot topic of recent research. In this thesis, we propose and demonstrate arrayed waveguide gratings (AWGs) based on a SiN platform as the multiplexers or demultiplexers. In the first chapter, we compare the material and waveguides between silicon and silicon nitride. We present numerical simulations of the SiN waveguides, including slab waveguides, strip waveguides, bent waveguides and tapered waveguides, using FDTD solutions and MODE solutions from Ansys Lumerical. These waveguides are used to form an AWG in this thesis. The influences of SiN AWGs designed parameters including focal length, separation of arrayed waveguides, gaps between adjacent apertures and propagation loss on the performances are studied based on a semi-analytical model. Common AWGs are typically designed in TE mode. In order to improve the transmission capacity in WDM system, in the second chapter, we present a polarization insensitive AWG built with SiN waveguides. The polarization insensitive AWGs are obtained when both the channel spacing and the center wavelength are aligned for TE and TM modes in a single AWG. The channel spacing polarization insensitivity is obtained by optimizing the geometry of the arrayed waveguides whereas the central wavelength polarization insensitivity is obtained by splitting the two polarization states and adjusting their angle of incidence at the input star coupler. A 100 GHz 1×8 AWG with crosstalk below −16 dB is demonstrated experimentally. In the design of SiN AWGs, the gaps of wider than 10 µm between adjacent identical waveguides are designed to minimize parasitic coupling. However, these gaps suppress further shrinking the footprint of AWGs. In the third chapter, we present an ultra-compact 100 GHz 1 × 8 SiN AWG enabled by a novel concept of the waveguide superlattice suppressing coupling between waveguides. Benefiting from the densely arrayed waveguides patterning with waveguide superlattice, this superlattice AWG has a compact footprint of 4.3 mm × 0.6 mm, which is more than two times smaller than a conventional AWG with similar performance. The SL-AWG also shows a low insertion loss of 3.4 dB and a low crosstalk level of −18 dB. Beside the coupling between waveguides discussed in the third chapter, the phase errors due to fabrication variations have a considerable impact on the performance of AWGs. It is shown that their performances are related to the length of arrayed waveguides determining the phase errors. However, there lacked a practical way to quantify the impact of arrayed waveguide length and fabrication variations on the performances of AWGs. In the fourth chapter, we present a statistical analysis of AWGs in presence of phase errors of arrayed waveguides. The important figures of merits including insertion loss, crosstalk and non-uniformity, are parameterized by the coherence length, a physical parameter that characterizes the accumulated phase errors in an optical waveguide. A die-level coherence length of 23.7 mm for the SiN waveguides is extracted by measuring variation of resonant wavelength of Mach-Zehnder interferometers. Through Monte Carlo simulations, we present the impacts of phase errors on performance of 1 × 4 AWGs with 200 GHz and 100 GHz channel spacings

System-on-Chip Design and Test with Embedded Debug Capabilities

In this project, I started with a System-on-Chip platform with embedded test structures. The baseline platform consisted of a Leon2 CPU, AMBA on-chip bus, and an Advanced Encryption Standard decryption module. The basic objective of this thesis was to use the embedded reconfigurable logic blocks for post-silicon debug and verification. The System-on-Chip platform was designed at the register transistor level and implemented in a 180-nm IBM process. Test logic instrumentation was done with DAFCA (Design Automation for Flexible Chip Architecture) Inc. pre-silicon tools. The design was then synthesized using the Synopsys Design Compiler and placed and routed using Cadence SOC Encounter. Total transistor count is about 3 million, including 1400K transistors for the debug module serving as on chip logic analyzer. Core size of the design is about 4.8mm x 4.8mm and the system is working at 151MHz. Design verification was done with Cadence NCSim. The controllability and observability of internal signals of the design is greatly increased with the help of pre-silicon tools which helps locate bugs and later fix them with the help of post-silicon tools. This helps prevent re-spins on several occasions thus saving millions of dollars. Post-silicon tools have been used to program assertions and triggers and inject numerous personalities into the reconfigurable fabric which has greatly increased the versatility of the circuit