Histogram Based Data Cryptographic Technique with High Level Security

Histogram shifting plays a major role in reversible data hiding technique. By this shifting method the distortion is reduced and the embedding capacity may be increased. This proposed work uses, shifting and embedding function. The pixel elements of the original image are divided into two disjoint groups. The first group is used to carry the secret data and the second group adds some additional information which ensures the reversibility of data. The  parameter such as PSNR, embedding capacity and bit rate are used for comparisons of various image

Study and Implementation of Image Compression using Different Wavelets

Transmission applications are utilized in broadcast,remote detecting by means of satellite, flying machine, radar, video chatting, PC interchanges, copy transmission, and so on. The cost of storage and transmission of images across a network is important now-a-days, as a huge collection of images in the form of databases are available on the Net. The reduction in file size is necessary to meet the bandwidth requirements for many transmission systems, and to reduce storage costs

DESIGN AND IMPLEMENTATION OF NON-UNIFORM QUANTIZERS FOR DISCRETE INPUT SAMPLES

This paper describes an algorithm for grayscale image compression based on non-uniform quantizers designed for discrete input samples. Non-uniform quantization is performed in two steps for unit variance, whereas design is done by introducing a discrete variance. The best theoretical and experimental results are obtained for those discrete values of variance which provide the operating range of quantizer located in the vicinity of maximal signal value that can appear on the entrance. The experiment is performed by applying proposed quantizers for compression of standard test grayscale images as a classic example of discrete input source. The proposed fixed non-uniform quantizers, designed for discrete input samples, provide up to 4.93 [dB] higher PSQNR compared to the fixed piecewise uniform quantizers designed for discrete input samples

Efficient architectures for multidimensional discrete transforms in image and video processing applications

PhD ThesisThis thesis introduces new image compression algorithms, their related architectures and data transforms architectures. The proposed architectures consider the current hardware architectures concerns, such as power consumption, hardware usage, memory requirement, computation time and output accuracy. These concerns and problems are crucial in multidimensional image and video processing applications. This research is divided into three image and video processing related topics: low complexity non-transform-based image compression algorithms and their architectures, architectures for multidimensional Discrete Cosine Transform (DCT); and architectures for multidimensional Discrete Wavelet Transform (DWT). The proposed architectures are parameterised in terms of wordlength, pipelining and input data size. Taking such parameterisation into account, efficient non-transform based and low complexity image compression algorithms for better rate distortion performance are proposed. The proposed algorithms are based on the Adaptive Quantisation Coding (AQC) algorithm, and they achieve a controllable output bit rate and accuracy by considering the intensity variation of each image block. Their high speed, low hardware usage and low power consumption architectures are also introduced and implemented on Xilinx devices. Furthermore, efficient hardware architectures for multidimensional DCT based on the 1-D DCT Radix-2 and 3-D DCT Vector Radix (3-D DCT VR) fast algorithms have been proposed. These architectures attain fast and accurate 3-D DCT computation and provide high processing speed and power consumption reduction. In addition, this research also introduces two low hardware usage 3-D DCT VR architectures. Such architectures perform the computation of butterfly and post addition stages without using block memory for data transposition, which in turn reduces the hardware usage and improves the performance of the proposed architectures. Moreover, parallel and multiplierless lifting-based architectures for the 1-D, 2-D and 3-D Cohen-Daubechies-Feauveau 9/7 (CDF 9/7) DWT computation are also introduced. The presented architectures represent an efficient multiplierless and low memory requirement CDF 9/7 DWT computation scheme using the separable approach. Furthermore, the proposed architectures have been implemented and tested using Xilinx FPGA devices. The evaluation results have revealed that a speed of up to 315 MHz can be achieved in the proposed AQC-based architectures. Further, a speed of up to 330 MHz and low utilisation rate of 722 to 1235 can be achieved in the proposed 3-D DCT VR architectures. In addition, in the proposed 3-D DWT architecture, the computation time of 3-D DWT for data size of 144×176×8-pixel is less than 0.33 ms. Also, a power consumption of 102 mW at 50 MHz clock frequency using 256×256-pixel frame size is achieved. The accuracy tests for all architectures have revealed that a PSNR of infinite can be attained

Data Hiding and Its Applications

Data hiding techniques have been widely used to provide copyright protection, data integrity, covert communication, non-repudiation, and authentication, among other applications. In the context of the increased dissemination and distribution of multimedia content over the internet, data hiding methods, such as digital watermarking and steganography, are becoming increasingly relevant in providing multimedia security. The goal of this book is to focus on the improvement of data hiding algorithms and their different applications (both traditional and emerging), bringing together researchers and practitioners from different research fields, including data hiding, signal processing, cryptography, and information theory, among others