11 research outputs found
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network
Bayesian optimization with Gaussian process as surrogate model has been
successfully applied to analog circuit synthesis. In the traditional Gaussian
process regression model, the kernel functions are defined explicitly. The
computational complexity of training is O(N 3 ), and the computation complexity
of prediction is O(N 2 ), where N is the number of training data. Gaussian
process model can also be derived from a weight space view, where the original
data are mapped to feature space, and the kernel function is defined as the
inner product of nonlinear features. In this paper, we propose a Bayesian
optimization approach for analog circuit synthesis using neural network. We use
deep neural network to extract good feature representations, and then define
Gaussian process using the extracted features. Model averaging method is
applied to improve the quality of uncertainty prediction. Compared to Gaussian
process model with explicitly defined kernel functions, the
neural-network-based Gaussian process model can automatically learn a kernel
function from data, which makes it possible to provide more accurate
predictions and thus accelerate the follow-up optimization procedure. Also, the
neural-network-based model has O(N) training time and constant prediction time.
The efficiency of the proposed method has been verified by two real-world
analog circuits
Autonomous Volterra algorithm for steady-state analysis of nonlinear circuits
published_or_final_versio
An automated design methodology of RF circuits by using Pareto-optimal fronts of EMsimulated inductors
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a singleobjective and a multiobjective optimization of a low noise amplifierMinisterio de Economía y Competitividad TEC2013-45638-C3-3-R, TEC2013-40430-RJunta de Andalucía PIC12-TIC-1481Consejo Superior de Investigaciones Científicas 201350E05
An Efficient Integrated Circuit Simulator And Time Domain Adjoint Sensitivity Analysis
In this paper, we revisit time-domain adjoint sensitivity with a circuit theoretic approach and an efficient solution is clearly stated in terms of device level. Key is the linearization of the energy storage elements (e.g., capacitance and inductance) and nonlinear memoryless elements (e.g., MOS, BJT DC characteristics) at each time step. Due to the finite precision of computation, numerical errors that accumulate across timesteps can arise in nonlinear elements
Optimization of Short-Channel RF CMOS Low Noise Amplifiers by Geometric Programming
Geometric programming (GP) is an optimization method to produce globally optimal circuit parameters with high computational efficiency. Such a method has been applied to short-channel (90 nm and 180 nm) CMOS Low Noise Amplifiers (LNAs) with common-source inductive degeneration to obtain optimal design parameters by minimizing the noise figure. An extensive survey of analytical models and experimental results reported in the literature was carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Geometric programming compatible functions have been determined to calculate the noise figure of short-channel CMOS devices by taking into consideration channel-length modulation and velocity saturation effects
Enhancing Variation-aware Analog Circuits Sizing
Today's analog design and verification face significant challenges due to circuit complexity and short time-to-market windows. Moreover, variations in design parameters have an adversely impact on the correctness and performance of analog circuits. Circuit sizing consists in determining the device sizes
and biasing voltages and currents such that the circuit satisfies its specifications. Traditionally, analog circuit sizing has been carried out by optimization-based methods, which of course will still be
important in the future. Unfortunately, these techniques cannot guarantee an exhaustive coverage of the design search space and hence, are not able to ensure the non-existence of higher quality design solutions. The sizing problem becomes more complicated and computationally expensive under
design parameters fluctuation. Indeed, existing yield analysis methods are computationally expensive and still encounter issues in problems with a high-dimensional process parameter space.
In this thesis, we present new approaches for enhancing variation-aware analog circuit sizing. The circuit sizing problem is encoded using nonlinear constraints. A new algorithm using Satisfiability
Modulo Theory (SMT) solving techniques exhaustively explores the analog design space and computes a continuous set of feasible sizing solutions. Next, a yield optimization stage aims to select the candidate design solution with the highest yield rate in the presence of process parameters variation.
For this purpose, a novel method for the computation of parametric yield is proposed. The method combines the advantages of sparse regression and SMT solving techniques. The key idea is to characterize the failure regions as a collection of hyperrectangles in the parameters space. The yield
estimation is based on a geometric calculation of probabilistic volumes subtended by the located hyperrectangles. The method can provide very large speed-up over Monte Carlo methods, when a high prediction accuracy is required. A new approach for improving analog yield optimization is also proposed. The optimization is performed in two steps. First, a global optimization phase samples the most potential optimal sub-regions of the feasible design space. The global search locates a design
point near the optimal solution. Second, a local optimization phase uses the near optimal solution as a starting point. Also, it constructs linear interpolating models of the yield to explore the basin of convergence and to reach the global optimum. We illustrate the efficiency of the proposed methods on various analog circuits. The application of the yield analysis method on an integrated ring oscillator and a 6T static RAM proves that it is suitable for handling problems with tens of process parameters
and can provide speedup of 5X-2000X over Monte Carlo methods. Furthermore, the application of our yield optimization methodology on the examples of a two-stage amplifier and a cascode amplifier shows that our approach can achieve higher quality in analog synthesis and unrivaled coverage of the analog design space when compared to traditional optimization techniques