DALI Bridge FPGA-Based Implementation in a Wireless Sensor Node for IoT Street Lighting Applications

Smart lighting systems based on the Digital Addressable Lighting Interface (DALI) protocol are the most suitable for street lighting systems, allowing digital lighting control operations. Unfortunately, the microcontrollers, which are commonly used in the Wireless Sensor Network nodes to control the lamps, do not implement this protocol. The DALI protocol implemented by software in the microcontroller consumes hardware resources (timers), processing time and requires a precise temporal analysis of the application, due to the strict bit times and the Manchester coding that it uses. In this work, the design of a bridge is proposed to free the microcontroller from the implementation of the DALI protocol. The novelty of this work is the implementation of the DALI Bridge in a low-cost Field-Programmable Gate Array (FPGA) with low power consumption. The bridge has been described in the hardware description language following the 1076-93 and 1076.3-97 standards, to guarantee its portability. The results of the synthesis show that a minimum amount of logical and routing resources is used, that the power consumption is in the order of tens of mW, that it has a very small latency time and that it supports a high operating frequency, which allows adding new functions. Its operation is verified by implementing a wireless sensor node using an FPGA of the Lattice Semiconductor iCE40 family

Analytical cost metrics: days of future past

2019 Summer.Includes bibliographical references.Future exascale high-performance computing (HPC) systems are expected to be increasingly heterogeneous, consisting of several multi-core CPUs and a large number of accelerators, special-purpose hardware that will increase the computing power of the system in a very energy-efficient way. Specialized, energy-efficient accelerators are also an important component in many diverse systems beyond HPC: gaming machines, general purpose workstations, tablets, phones and other media devices. With Moore's law driving the evolution of hardware platforms towards exascale, the dominant performance metric (time efficiency) has now expanded to also incorporate power/energy efficiency. This work builds analytical cost models for cost metrics such as time, energy, memory access, and silicon area. These models are used to predict the performance of applications, for performance tuning, and chip design. The idea is to work with domain specific accelerators where analytical cost models can be accurately used for performance optimization. The performance optimization problems are formulated as mathematical optimization problems. This work explores the analytical cost modeling and mathematical optimization approach in a few ways. For stencil applications and GPU architectures, the analytical cost models are developed for execution time as well as energy. The models are used for performance tuning over existing architectures, and are coupled with silicon area models of GPU architectures to generate highly efficient architecture configurations. For matrix chain products, analytical closed form solutions for off-chip data movement are built and used to minimize the total data movement cost of a minimum op count tree

A hardware-software codesign framework for cellular computing

Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through hardware mechanisms such as super-scalar execution. However, both these approaches seem to have reached a plateau, mainly due to issues related to design complexity and cost-effectiveness. To face the stabilization of performance of single-threaded processors, the current trend in processor design seems to favor a switch to coarser-grain parallelization, typically at the thread level. In other words, high computational power is achieved not only by a single, very fast and very complex processor, but through the parallel operation of several processors, each executing a different thread. Extrapolating this trend to take into account the vast amount of on-chip hardware resources that will be available in the next few decades (either through further shrinkage of silicon fabrication processes or by the introduction of molecular-scale devices), together with the predicted features of such devices (e.g., the impossibility of global synchronization or higher failure rates), it seems reasonable to foretell that current design techniques will not be able to cope with the requirements of next-generation electronic devices and that novel design tools and programming methods will have to be devised. A tempting source of inspiration to solve the problems implied by a massively parallel organization and inherently error-prone substrates is biology. In fact, living beings possess characteristics, such as robustness to damage and self-organization, which were shown in previous research as interesting to be implemented in hardware. For instance, it was possible to realize relatively simple systems, such as a self-repairing watch. Overall, these bio-inspired approaches seem very promising but their interest for a wider audience is problematic because their heavily hardware-oriented designs lack some of the flexibility achievable with a general purpose processor. In the context of this thesis, we will introduce a processor-grade processing element at the heart of a bio-inspired hardware system. This processor, based on a single-instruction, features some key properties that allow it to maintain the versatility required by the implementation of bio-inspired mechanisms and to realize general computation. We will also demonstrate that the flexibility of such a processor enables it to be evolved so it can be tailored to different types of applications. In the second half of this thesis, we will analyze how the implementation of a large number of these processors can be used on a hardware platform to explore various bio-inspired mechanisms. Based on an extensible platform of many FPGAs, configured as a networked structure of processors, the hardware part of this computing framework is backed by an open library of software components that provides primitives for efficient inter-processor communication and distributed computation. We will show that this dual software–hardware approach allows a very quick exploration of different ways to solve computational problems using bio-inspired techniques. In addition, we also show that the flexibility of our approach allows it to exploit replication as a solution to issues that concern standard embedded applications

Chapter SW Annotation Techniques and RTOS Modelling for Native Simulation of Heterogeneous Embedded Systems

Space scienc

Viability of FPGAs in wireless sensor networks

Dentro del contexto del proyecto de tesis planteado, se aborda el problema del control y las comunicaciones en las luminarias de los sistemas inteligentes de alumbrado público. En los trabajos reportados en la literatura sobre el tema planteado, se encuentra el problema particular de la implementación de protocolos digitales de comunicaciones en las luminarias, y especialmente en la implementación del protocolo Digital Addressable Lighting Interface (DALI) en redes de sensores inalámbricos. Desafortunadamente los microcontroladores que habitualmente se emplean en los nodos de sensores inalámbricos, no integran periféricos para este tipo de protocolos, por lo que suelen implementarse por software. Un punto de oportunidad es implementar este tipo de protocolos en hardware mediante una FPGA y de esta forma demostrar su viabilidad en nodos de sensores inalámbricos. En esta tesis se presenta una solución para implementar por hardware el protocolo DALI para controlar sistemas de iluminación inteligente. La novedad de este trabajo es la descripción portable del protocolo DALI implementado en forma de un bridge de comunicaciones en una FPGA de bajo coste, bajo consumo de energía y poca cantidad de recursos lógicos, para ser embebida en un nodo sensor inalámbrico. El protocolo se ha descrito en lenguaje VHDL siguiendo los estándares 1076-93 y 1076.3-97. Las contribuciones de este trabajo demuestran la viabilidad de la utilización de FPGAs en redes de sensores inalámbricos, que en este caso se utilizan para implementar el bridge DALI y resolver el problema de la interfaz de comunicación.Within the context of the proposed thesis project, the problem of control and communications for luminaires in intelligent public lighting systems is addressed. In the works reported in the literature on the subject, we can find the particular problem of the implementation of digital communication protocols for luminaires, and specifically the implementation of the Digital Addressable Lighting Interface (DALI) protocol in wireless sensor networks. Unfortunately, the microcontrollers that are commonly used in wireless sensor nodes do not integrate peripherals for this type of protocol, so they are usually implemented by software. A point of opportunity is to implement this type of protocols in hardware through an FPGA and thus demonstrate its viability in wireless sensor nodes. In this thesis, a solution is presented to implement the DALI protocol by hardware to control intelligent lighting systems. The novelty of this work is the portable description of the DALI protocol implemented in the form of a communications bridge in a low-cost FPGA, with low power consumption and few logical resources, which will be embedded in a wireless sensor node. The protocol has been described in VHDL language following the 1076-93 and 1076.3-97 standards. The contributions of this work demonstrate the feasibility of using FPGAs in wireless sensor networks, which in this case are used to implement the DALI bridge and solve the communication interface problem

Développement d'une méthodologie de codesign matériel/logiciel pour des applications de communications à haute vitesse

Définition du codesign -- Application utilisée pour valider la méthodologie -- Les différentes étapes du codesign -- Les différents composants du partitionnement -- Description des estimateurs utilisés -- Estimateurs pour la partie logicielle -- Estimateurs pour la partie matérielle -- Estimation et modèle de communications -- La fonction objectif -- Les algorithmes de partitionnement -- Introduction à la technologie XDSL -- Méthodologie utilisée et résultats -- Spécifiactions du systèmes et défnition des blocs -- Description des blocs pour le logiciel et le matériel -- Développement de la dissipation de puissance pour le logiciel -- Estimation du temps d'exécution logiciel -- Estimation de la surface et du temps d'exécution du matériel -- Estimation de la dissipation de puissance pour la partie matérielle -- Estimation des communications -- Algorithme de partitionnement -- Le meilleur partitionnement pour le Universal ADSL -- Implantation de mécanismes de communications -- Implantation de canaux de communications -- Co-simulation matérielle/logicielle

MiADL : linguagem para geração automática de simuladores redireccionáveis

Tese de Doutoramento em Electrónica Industrial - Área de Conhecimento em Informática IndustrialOs sistemas embutidos, além de fazerem cada vez mais parte da vida do cidadão comum, são dispositivos cada vez mais sofisticados e complexos. As equipas de desenvolvimento de sistemas embutidos têm por isso de lidar com complexidade crescente para atingir performances e requisitos cada vez mais exigentes (ex. hierarquias de memória complexas). Estes dispositivos exigem ferramentas de software – tais como: simuladores, depuradores, assembladores ou compiladores – que têm que acompanhar a evolução dos mesmos. Torna-se por isso fundamental desenvolver de forma rápida o conjunto de ferramentas para determinado sistema embutido para garantir espaço num mercado bastante competitivo, ou seja, conseguir um curto time-tomarket. O desenvolvimento de aplicações que permitam a rápida e eficaz geração deste tipo de ferramentas assume relevo no âmbito do desenvolvimento dos sistemas embutidos. Das ferramentas de software, o simulador é uma das essenciais para o desenvolvimento de novas arquitecturas computacionais. Entre as vantagens que apresenta, destaca-se a flexibilidade e baixo custo, uma vez que permite simular hardware em estágios iniciais do processo de desenvolvimento, sem necessidade de existência física do mesmo. Os primeiros simuladores eram desenvolvidos manualmente. Entretanto têm emergido linguagens de descrição de arquitecturas (ADLs) que facilitam a geração dessas ferramentas de uma forma automática, rápida, redireccionável e menos propensa a erros. Uma das vantagens destas linguagens consiste em permitirem gerar várias ferramentas a partir de uma única descrição, o que garante desde logo compatibilidade e coerência entre elas. Estas linguagens além de aplicação prática para fins industriais, podem também ser usadas para fins educacionais nomeadamente para o ensino de arquitecturas de microprocessadores. Este trabalho de Doutoramento tem por objectivo contribuir para simplificar o processo de construção de simuladores, usados no projecto de sistemas embutidos. Pretende-se mostrar que a melhor forma de alcançar este objectivo consiste numa abordagem usando uma linguagem estruturada e que explora os comportamentos/sintaxes comuns ao conjunto de instruções da arquitectura alvo. Para suportar esta abordagem propõem-se uma linguagem que introduz uma forma diferente de descrever arquitecturas do conjunto de instruções (ISAs). A linguagem nomeada de Minho Architecture Description Language (MiADL), possui uma estrutura que explora o que é comum às instruções (comportamento e assembly) e permite a existência de blocos que são descritos uma vez e podem ser usados várias vezes. Desta forma a validação e identificação de incoerências fica facilitada e conduz a descrições claras, robustas e fáceis de depurar. As principais características desta linguagem são a existência de scopes, a inferência de argumentos, a estrutura em secções que permitem reutilização em diferentes partes da linguagem, a forma como lida com variabilidades e regularidades presentes em ISAs e a relação com a informação presente geralmente em manuais dos processadores. As modelações usando MiADL de vários ISAs complexos, de arquitecturas conhecidas, resulta em descrições bastante compactas, estruturadas e fáceis de explorar, quando comparadas com as conseguidas por outras ADLs. Em termos de simulação, com base em modelações MiADL, na tese é apresentada a infra-estrutura de geração automática de simuladores redireccionáveis de ISAs usando a técnica de simulação compilada estática, recorrendo a generic programming. Esta possibilidade de recorrer àquela técnica de programação deve-se às características da linguagem, que com outras ADLs não é tão fácil de conseguir. Além de tornar o código mais compacto e estruturado, permite que o compilador nativo explore optimizações para conseguir bom desempenho do simulador.Embedded system devices, besides having a growing importance in the common citizen’s life, are more and more sophisticated and complex devices. The embedded systems development teams have to deal with the rising complexity to provide higher performance and more demanding requisites (ex. complex memory organizations). These devices require software tools – such as: simulator, debugger, linker, assembler or compiler - that must be proper to those devices. It is therefore essential to develop in a quick way the software toolkit, for the target embedded system, to assure place in a competitive market, in other words, to shorten time-to-market. The development of applications to efficiently generate the software toolkit is of great importance in the embedded systems development scenario. From the set of software tools, the simulator is an essential tool for the development of new computational architectures. It brings flexibility and reduces the cost, since it allows the hardware simulation in early stages of the development process, without the physical existence of such hardware. The first simulators were hand-coded developed. Since then, new Architecture Description Languages (ADLs) have emerged, that have made easier the generation of these tools in an automatic, quicker, retargetable and error resilient way. One advantage of these languages is that they allow generating several tools from a single description. These languages, besides the practical applications for industrial purposes, can also be used for educational purposes namely for teaching microprocessors architectures. The purpose of this PhD work is to contribute for the simplification of generating simulators to be used in the design of embedded systems. The aim is to demonstrate that the best way is achieved through the use of a structured language which explores the common behavioural/syntaxes of the target instruction set architecture. To support this approach a new language is proposed which introduces a new way to describe Instructions Set Architectures (ISAs). This language, named Minho Architecture Description Language (MiADL), possesses a structure that explores what is common with the instructions (behaviour and assembly) and is block organized. The language blocks can be described once and used several times. In this way the validation and detection of incoherencies is facilitated, leading to clear, robust and easy to debug descriptions. The main features of this language are: scopes existence; arguments inference; structure organized in sections which allows its reuse in different parts of the description; the way in which it deals with variability and regularities present in complex ISAs and similarity with the information usually available in processors manuals. The descriptions of several complex ISAs of known architectures using MiADL, result in rather compact, structured and easy to explore descriptions, when compared with the ones obtained by other ADLs. In this thesis is also discussed the retargetable framework designed for automatic generation of compiled simulators, from MiADL descriptions, using generic programming to execute instruction behaviors. The use of function templates is possible due to MiADL features, with other ADLs this isn’t so easy to accomplish. Besides making the code more compact and structured, allows to explore optimizations from the native compiler to achieve improvements in the simulator´s performace.Ministério da Educação - Prodep II

Customising compilers for customisable processors

The automatic generation of instruction set extensions to provide application-specific acceleration for embedded processors has been a productive area of research in recent years. There have been incremental improvements in the quality of the algorithms that discover and select which instructions to add to a processor. The use of automatic algorithms, however, result in instructions which are radically different from those found in conventional, human-designed, RISC or CISC ISAs. This has resulted in a gap between the hardware’s capabilities and the compiler’s ability to exploit them. This thesis proposes and investigates the use of a high-level compiler pass that uses graph-subgraph isomorphism checking to exploit these complex instructions. Operating in a separate pass permits techniques to be applied that are uniquely suited for mapping complex instructions, but unsuitable for conventional instruction selection. The existing, mature, compiler back-end can then handle the remainder of the compilation. With this method, the high-level pass was able to use 1965 different automatically produced instructions to obtain an initial average speed-up of 1.11x over 179 benchmarks evaluated on a hardware-verified cycle-accurate simulator. This result was improved following an investigation of how the produced instructions were being used by the compiler. It was established that the models the automatic tools were using to develop instructions did not take account of how well the compiler could realistically use them. Adding additional parameters to the search heuristic to account for compiler issues increased the speed-up from 1.11x to 1.24x. An alternative approach using a re-designed hardware interface was also investigated and this achieved a speed-up of 1.26x while reducing hardware and compiler complexity. A complementary, high-level, method of exploiting dual memory banks was created to increase memory bandwidth to accommodate the increased data-processing bandwidth provided by extension instructions. Finally, the compiler was considered for use in a non-conventional role where rather than generating code it is used to apply source-level transformations prior to the generation of extension instructions and thus affect the shape of the instructions that are generated