Hardware/Software Co-design of Communication Protocols

An important aspect in providing high performance distributed systems such as multimedia systems is the combined use of hardware and software in the end systems. System design techniques should allow hardware/software co-design to integrate both means of implementation. In this paper, we show how the standardized formal language Estelle can be used to facilitate co-design. The system will first be designed in Estelle. At the point in time of final decision on which parts to implement in software and which in hardware, the original specification will be split into several partial specifications. The software parts are translated into C code, while the hardware parts are translated into VHDL code for further analysis and development. We present a tool environment which supports the protocol developer in the design and implementation process. A simple Video-on-Demand example shows the usefulness of the tool environment

Hardware/Software Co-Design via Specification Refinement

System-level design is an engineering discipline focused on producing methods, technologies, and tools that enable the specification, design, and implementation of complex, multi-discipline, and multi-domain systems. System-level specifications are as abstract as possible, defining required system behaviors while eliding implementation details. These implementation details must be added during the implementation process and the high effort associated with this locks system engineers onto the chosen implementation architecture. This work provides two contributions that ease the implementation process. The Rosetta synthesis capability generates hardware/software co-designed implementations from specifications that contain low level implementation details. The Rosetta refinement capability extends this by allowing a system's functional behavior and its implementation details to be described separately. The Rosetta Refinement Tool combines the functional behavior and the implementation details to form a system specification that can be synthesized using the Rosetta synthesis capability. The Rosetta refinement capability is exposed using existing Rosetta language constructs that have, previous to this work, never been exploited. Together these two capabilities allow the refinement of high level, architecture independent specifications into low level, architecture specific hardware/software co-designed implementations. The result is an effective platform for rapid prototyping of hardware/software co-designs and provides system engineers with the novel ability to explore different system architectures with low effort

Hardware/Software Co-design for Multicore Architectures

Siirretty Doriast

Hardware-Software Co-Design for Fingerprint Biometric Identification

This paper describes the design of a specific architecture for fingerprint identification based on a hardware-software co-design. This work summarizes the main stages involved in a classical fingerprint feature extraction algorithm. The paper proposes a hardware-software partitioning based on a profiler deduced from the execution of the whole algorithm running in a Pentium 1.7 GHz

Hardware-Software Co-Design for Network Performance Measurement

Diagnosing performance problems in networks is important, for example to determine where packets experience high latency or loss. However, existing performance diagnoses are constrained by limited switch mechanisms for measurement. Alternatively, operators use endpoint information indirectly to infer root causes for problematic latency or drops. Instead of designing piecemeal solutions to work around such switch restrictions, we believe that the right approach is to co-design language abstractions and switch hardware primitives for network performance measurement. This approach provides confidence that the switch primitives are sufficiently general, i.e., they can support a variety of existing and unanticipated use cases. We present a declarative query language that allows operators to ask a diverse set of network performance questions. We show that these queries can be implemented efficiently in switch hardware using a novel programmable key-value store primitive. Our preliminary evaluations show that our hardware design is feasible at modest chip area overhead relative to existing switching chips

Hardware-software co-design of AES on FPGA

This paper presents a compact hardware-software co-design of Advanced Encryption Standard (AES) on the field programmable gate arrays (FPGA) designed for low-cost embedded systems. The design uses MicroBlaze, a soft-core processor from Xilinx. The computationally intensive operations of the AES are implemented in hardware for better speed. The sub-byte calculation is designed with the help of the processor carrying out the calculations using hardware blocks implemented using FPGA. By incorporating the processor in the AES design, the total number of slices required to implement the AES algorithm on FPGA is proved to be reduced. The entire AES system design is validated using 460 slices in Spartan-3E XC3S500E, which is one of the low-cost FPGA