Adjustable compression method for still JPEG images

There are a large number of image processing applications that work with different performance requirements and available resources. Recent advances in image compression focus on reducing image size and processing time, but offer no real-time solutions for providing time/quality flexibility of the resulting image, such as using them to transmit the image contents of web pages. In this paper we propose a method for encoding still images based on the JPEG standard that allows the compression/decompression time cost and image quality to be adjusted to the needs of each application and to the bandwidth conditions of the network. The real-time control is based on a collection of adjustable parameters relating both to aspects of implementation and to the hardware with which the algorithm is processed. The proposed encoding system is evaluated in terms of compression ratio, processing delay and quality of the compressed image when compared with the standard method

I Simulatori in realtà virtuale: un ausilio nella formazione chirurgica

Negli ultimi anni la necessità di formazione in campo laparoscopico ha spinto verso la creazione di simulatori chirurgici di diversa fattura e diversa complessità. Al momento molti di questi sono disponibili in commercio. Ognuna di questi ha il proprio design, struttura e programma di formazione. L'evoluzione è rappresentata dall’utilizzo della Realtà Virtuale, che mima l'azione reale e lavora sulle diverse competenze acquisite durante i corsi di formazione e l’esperienza chirurgica al campo operatorio. Il ruolo della formazione "sicura ed efficiente" è necessario nel corso di una specializzazione in chirurgia e durante la formazione continua. La simulazione in realtà virtuale è in grado di offrire un numero infinito di scenari chirurgici. I simulatori chirurgici in realtà virtuale di ultima generazione sono forniti di percorsi di formazione graduali che guidano lo specializzando nell’acquisizione di manualità “fine” nei singoli tasks fino alla procedura completa “full task” di un intervento chirurgico, ad esempio una colecistectomia. In questo studio abbiamo voluto testare la validità di un’acquisizione graduale di tecnica manuale “step by step” rispetto all’esercizio diretto solo su una procedura completa mediante l’ausilio di un simulatore in Virtual Reality, il LapMentor®(Simbionix,Israele). Specializzandi in Chirurgia Generale privi di esperienza precedente in laparoscopia hanno ottenuto risultati migliori sulla procedura completa della colecistectomia laparoscopica procedendo durante il corso step by step rispetto a coloro che hanno eseguito la procedura completa “full task” direttamente. Il nostro studio conferma che una buona esperienza e la conoscenza delle capacità tecniche di base nel campo della formazione laparoscopica migliorano le prestazioni nella procedura completa.In the last years the need for training in laparoscopy has led to the creation of surgical simulators of varying complexity and different bill. Currently, many of these are commercially available. Each of these has its own design, structure and training program. The trend is the use of virtual reality, which mimics the real action and work on various skills acquired during the training and experience in the surgical operating field. The role of training on safe and efficient "is necessary in the course of specialization in surgery and during the training. The simulation in virtual reality is able to offer an infinite number of surgical scenarios. The surgical simulators in virtual reality are equipped with the latest training courses that guide the gradual specializing in the acquisition of manual skills "end" in the individual tasks to complete procedure "full task" for surgery, such as a cholecystectomy. In this study we wanted to test the validity of the gradual acquisition of technical manual "step by step" only on a direct comparison with the whole procedure with the help of a mortgage in Virtual Reality, the LapMentor ® (Simbionix, Israel) .Specializing in general surgery with no previous experience in laparoscopy have performed better on the whole procedure of laparoscopic cholecystectomy during the course of proceeding step by step than those who performed the procedure complete "full task" directly. Our study confirms that a good experience and knowledge of basic technical skills in training laparoscopic improve performance in the whole procedure

MINIMIZATION OF RESOURCE UTILIZATION FOR A REAL-TIME DEPTH-MAP COMPUTATIONAL MODULE ON FPGA

Depth-map algorithm allows camera system to estimate depth in many applications. The algorithm is computationally intensive and therefore more effective to be implemented on hardware such as the Field Programmable Gate Array (FPGA). However, the recurring issue in FPGA implementation is the resource limitation. The issue is normally resolved by modifying the algorithm. However, the issue can also be addressed by implementing hardware architectures without the need to modify the depth-map algorithm. In this thesis, five different depth-map processor architectures for the sum-of-absolute-difference (SAD) depth-map algorithm on FPGA at real-time were designed and implemented. Two resource minimization techniques were employed to address the resource limitation issues. Resource usage and performance of these architectures were compared. Memory contention and bandwidth constrain were resolved by using self-initiative memory controller, FIFOs and line buffers. Parallel processing was utilized to achieve high processing speed at low clock frequency. Memory-based line buffers were used instead of register-based line buffers to save 62.4% of logic element (LEs) used, but require some additional dedicated memory bits. A proper use of registers to replace repetitive subtractors saves 24.75% of LEs. The system achieves SAD performance of 295 mega pixel disparity per second (MPDS) for the architecture with 640x480 pixel image, 3x3 pixel window size, 32 pixel disparity range and 30 frames per second. The system achieves SAD performance of 590 MPDS for the 64 pixels disparity range architecture. The disparity matching module works at the frequency of 10 MHz and produces one pixel of result every clock cycle. The results are dense disparity images, suitable for high speed, low cost, low power applications

Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications

This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The software developed for IP image compression achieves high quality ratios over classic methodologies by exploiting the inherent redundancy that is present in IP images. However, there are certain time constraints to the software approach that must be confronted in order to address real-time applications. Our main effort is to achieve real-time performance by implementing in hardware the most time-consuming parts of the compression algorithm. The proposed novel digital architecture features minimized memory read operations and extensive simultaneous processing, while taking into concern the memory and data bandwidth limitations of a single FPGA implementation. Our results demonstrate that the implemented hardware system can successfully process high resolution IP video sequences in real-time, addressing a vast range of applications, from mobile systems to demanding desktop displays. © 2007 Elsevier Inc. All rights reserved

MINIMIZATION OF RESOURCE UTILIZATION FOR A REAL-TIME DEPTH-MAP COMPUTATIONAL MODULE ON FPGA

Depth-map algorithm allows camera system to estimate depth in many applications. The algorithm is computationally intensive and therefore more effective to be implemented on hardware such as the Field Programmable Gate Array (FPGA). However, the recurring issue in FPGA implementation is the resource limitation. The issue is normally resolved by modifying the algorithm. However, the issue can also be addressed by implementing hardware architectures without the need to modify the depth-map algorithm. In this thesis, five different depth-map processor architectures for the sum-of-absolute-difference (SAD) depth-map algorithm on FPGA at real-time were designed and implemented. Two resource minimization techniques were employed to address the resource limitation issues. Resource usage and performance of these architectures were compared. Memory contention and bandwidth constrain were resolved by using self-initiative memory controller, FIFOs and line buffers. Parallel processing was utilized to achieve high processing speed at low clock frequency. Memory-based line buffers were used instead of register-based line buffers to save 62.4% of logic element (LEs) used, but require some additional dedicated memory bits. A proper use of registers to replace repetitive subtractors saves 24.75% of LEs. The system achieves SAD performance of 295 mega pixel disparity per second (MPDS) for the architecture with 640x480 pixel image, 3x3 pixel window size, 32 pixel disparity range and 30 frames per second. The system achieves SAD performance of 590 MPDS for the 64 pixels disparity range architecture. The disparity matching module works at the frequency of 10 MHz and produces one pixel of result every clock cycle. The results are dense disparity images, suitable for high speed, low cost, low power applications