Towards FPGA Emulation of Fiber-Optic Channels for Deep-BER Evaluation of DSP Implementations

We introduce an FPGA-based fiber-optic channel emulator, including both AWGN and carrier phase noise, which can be used to perform deep-BER simulations of DSP implementations and accurately evaluate DSP implementation penalties

Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations

Using FPGA-accelerated simulations, we study the cycle-slip rate of 16QAM blind phase search implementations. While block averaging suffers from degraded BER when compared to sliding-window averaging, it results in lower cycle-slip rates and power dissipation