Highly efficient Localisation utilising Weightless neural systems

Efficient localisation is a highly desirable property for an autonomous navigation system. Weightless neural networks offer a real-time approach to robotics applications by reducing hardware and software requirements for pattern recognition techniques. Such networks offer the potential for objects, structures, routes and locations to be easily identified and maps constructed from fused limited sensor data as information becomes available. We show that in the absence of concise and complex information, localisation can be obtained using simple algorithms from data with inherent uncertainties using a combination of Genetic Algorithm techniques applied to a Weightless Neural Architecture

Evolvable Reconfigurable Hardware Framework for Edge Detection

Systems on Reconfigurable Chips contain rich resources of logic, memory, and processor cores on the same fabric. This platform is suitable for implementation of Evolvable Reconfigurable Hardware Architectures (ERHA). It is based on the idea of combining reconfigurable Field Programmable Gate Arrays (FPGA) along with genetic algorithms (GA) to perform the reconfiguration operation. This architecture is a suitable candidate for implementation of early-processing stage operators of image processing such as filtering and edge detection. However, there are still fundamental issues need to be solved regarding the on-chip reprogramming of the logic. This paper presents a framework for implementing an evolvable hardware architecture for edge detection on Xilinx Virtex–4 chip. Some preliminary results are discussed

Pipelined genetic propagation

© 2015 IEEE.Genetic Algorithms (GAs) are a class of numerical and combinatorial optimisers which are especially useful for solving complex non-linear and non-convex problems. However, the required execution time often limits their application to small-scale or latency-insensitive problems, so techniques to increase the computational efficiency of GAs are needed. FPGA-based acceleration has significant potential for speeding up genetic algorithms, but existing FPGA GAs are limited by the generational approaches inherited from software GAs. Many parts of the generational approach do not map well to hardware, such as the large shared population memory and intrinsic loop-carried dependency. To address this problem, this paper proposes a new hardware-oriented approach to GAs, called Pipelined Genetic Propagation (PGP), which is intrinsically distributed and pipelined. PGP represents a GA solver as a graph of loosely coupled genetic operators, which allows the solution to be scaled to the available resources, and also to dynamically change topology at run-time to explore different solution strategies. Experiments show that pipelined genetic propagation is effective in solving seven different applications. Our PGP design is 5 times faster than a recent FPGA-based GA system, and 90 times faster than a CPU-based GA system

Generalized disjunction decomposition for the evolution of programmable logic array structures

Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

SHADHO: Massively Scalable Hardware-Aware Distributed Hyperparameter Optimization

Computer vision is experiencing an AI renaissance, in which machine learning models are expediting important breakthroughs in academic research and commercial applications. Effectively training these models, however, is not trivial due in part to hyperparameters: user-configured values that control a model's ability to learn from data. Existing hyperparameter optimization methods are highly parallel but make no effort to balance the search across heterogeneous hardware or to prioritize searching high-impact spaces. In this paper, we introduce a framework for massively Scalable Hardware-Aware Distributed Hyperparameter Optimization (SHADHO). Our framework calculates the relative complexity of each search space and monitors performance on the learning task over all trials. These metrics are then used as heuristics to assign hyperparameters to distributed workers based on their hardware. We first demonstrate that our framework achieves double the throughput of a standard distributed hyperparameter optimization framework by optimizing SVM for MNIST using 150 distributed workers. We then conduct model search with SHADHO over the course of one week using 74 GPUs across two compute clusters to optimize U-Net for a cell segmentation task, discovering 515 models that achieve a lower validation loss than standard U-Net.Comment: 10 pages, 6 figure

Towards hardware acceleration of neuroevolution for multimedia processing applications on mobile devices

This paper addresses the problem of accelerating large artificial neural networks (ANN), whose topology and weights can evolve via the use of a genetic algorithm. The proposed digital hardware architecture is capable of processing any evolved network topology, whilst at the same time providing a good trade off between throughput, area and power consumption. The latter is vital for a longer battery life on mobile devices. The architecture uses multiple parallel arithmetic units in each processing element (PE). Memory partitioning and data caching are used to minimise the effects of PE pipeline stalling. A first order minimax polynomial approximation scheme, tuned via a genetic algorithm, is used for the activation function generator. Efficient arithmetic circuitry, which leverages modified Booth recoding, column compressors and carry save adders, is adopted throughout the design