Penerapan Floating Point Unit Sebagai Co-processor Yang Diimplementasikan Dengan Menggunakan FPGA

Sirkuit aritmatika merupakan bagian penting dari sistem digital. Dengan kemajuan luar biasa dalam VLSI, banyak sirkuit yang kompleks, yang kemarin tak terpikirkan menjadi mudah terealisasi saat ini.Dalam skripsi ini unit aritmatika bekerja berdasarkan standar IEEE 754 untuk bilangan floating point presisi tunggal telah diimplementasikan pada FPGA Spartan 3E. Unit aritmatika yang diimplementasikan memiliki unit pengolahan 32 bit yang mampu untuk melakukan operasi aritmatika seperti, penjumlahan, pengurangan, perkalian dan pembagian serta mampu menangani operasi perhitungan khusus yang tidak bisa dikerjakan oleh model operasi standar. Sintesis FPGA untuk unit aritmatika dilakukan dengan menggunakan Xilinx ISE 11.1.Hasilnya unit aritmatika ini mampu bekerja menghitung dua buah bilangan floating point presisi tunggal standar IEEE 754 dengan waktu yang dibutuhkan sebesar 233.689ns. Kata Kunci— Floating Point, FPGA, Standar IEEE 754, Unit Aritmatika, Operasi Aritmatika

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm

To overcome the limitations of conventional floating-point number formats, an interval arithmetic and variable-width storage format called universal number (unum) has been recently introduced. This paper presents the first (to the best of our knowledge) silicon implementation measurements of an application-specific integrated circuit (ASIC) for unum floating-point arithmetic. The designed chip includes a 128-bit wide unum arithmetic unit to execute additions and subtractions, while also supporting lossless (for intermediate results) and lossy (for external data movements) compression units to exploit the memory usage reduction potential of the unum format. Our chip, fabricated in a 65 nm CMOS process, achieves a maximum clock frequency of 413 MHz at 1.2 V with an average measured power of 210 uW/MHz

Radix Conversion for IEEE754-2008 Mixed Radix Floating-Point Arithmetic

Conversion between binary and decimal floating-point representations is ubiquitous. Floating-point radix conversion means converting both the exponent and the mantissa. We develop an atomic operation for FP radix conversion with simple straight-line algorithm, suitable for hardware design. Exponent conversion is performed with a small multiplication and a lookup table. It yields the correct result without error. Mantissa conversion uses a few multiplications and a small lookup table that is shared amongst all types of conversions. The accuracy changes by adjusting the computing precision

Measuring Improvement when Using HUB Formats to Implement Floating-Point Systems under Round-to-Nearest

MEC bajo TIN2013-42253-PThis paper analyzes the benefits of using HUB formats to implement floating-point arithmetic under round-tonearest mode from a quantitative point of view. Using HUB formats to represent numbers allows the removal of the rounding logic of arithmetic units, including sticky-bit computation. This is shown for floating-point adders, multipliers, and converters. Experimental analysis demonstrates that HUB formats and the corresponding arithmetic units maintain the same accuracy as conventional ones. On the other hand, the implementation of these units, based on basic architectures, shows that HUB formats simultaneously improve area, speed, and power consumption. Specifically, based on data obtained from the synthesis, a HUB single-precision adder is about 14% faster but consumes 38% less area and 26% less power than the conventional adder. Similarly, a HUB single-precision multiplier is 17% faster, uses 22% less area, and consumes slightly less power than conventional multiplier. At the same speed, the adder and multiplier achieve area and power reductions of up to 50% and 40%, respectively

Interval Slopes as Numerical Abstract Domain for Floating-Point Variables

The design of embedded control systems is mainly done with model-based tools such as Matlab/Simulink. Numerical simulation is the central technique of development and verification of such tools. Floating-point arithmetic, that is well-known to only provide approximated results, is omnipresent in this activity. In order to validate the behaviors of numerical simulations using abstract interpretation-based static analysis, we present, theoretically and with experiments, a new partially relational abstract domain dedicated to floating-point variables. It comes from interval expansion of non-linear functions using slopes and it is able to mimic all the behaviors of the floating-point arithmetic. Hence it is adapted to prove the absence of run-time errors or to analyze the numerical precision of embedded control systems