System for Configuring Modular Telemetry Transponders

A system for configuring telemetry transponder cards uses a database of error checking protocol data structures, each containing data to implement at least one CCSDS protocol algorithm. Using a user interface, a user selects at least one telemetry specific error checking protocol from the database. A compiler configures an FPGA with the data from the data structures to implement the error checking protocol

Secure Communication Using Non-systematic Error Control Codes

A transmitter device (110T) for secure communication includes: an encoder (170) configured to apply a non-systematic error correcting code (NS ECC) to a message, thus producing encoded bits with no clear message bits; and a transceiver (720) configured to transmit the encoded bits over a main channel to a receiver. A method for secure communication includes: encoding a message with an NS ECC to produce an encoded message carrying no message bits in the clear; and transmitting the encoded message over a main channel (120). The NS ECC characteristics result in an eavesdropper channel error probability under a security threshold (320) and a main channel error probability over a reliability threshold (310), whenever an eavesdropper (140) listening on an eavesdropper channel (150) is more than distance Z (220) from the transmitter. Unreliable bits in the encoded bits render the eavesdropper unable to reliably decode messages on the main channel.Georgia Tech Research CorporationKorea Advanced Institute Of Science And Technolog

Reconfigurable Sensor Monitoring System

A reconfigurable sensor monitoring system includes software tunable filters, each of which is programmable to condition one type of analog signal. A processor coupled to the software tunable filters receives each type of analog signal so-conditioned

Високопродуктивні АЦП із ваговою надлишковістю зі змінними тривалостями тактів порозрядного кодування

У монографії розглянуто питання побудови високопродуктивних АЦП із ваговою надлишковістю та змінними тривалостями тактів порозрядного наближення. У роботі досліджуються запропоновані методи підвищення продуктивності порозрядних АЦП із ваговою надлишковістю. Книга розрахована на науковців, аспірантів та інженерів, які займаються розробкою високоточних швидкодіючих аналого-цифрових перетворювачів.В монографии рассмотрены вопросы построения высокопроизводительных АЦП с весовой избыточностью и переменной длительности тактов поразрядного приближения. В работе исследуются предложеные методы повышения производительности поразрядных АЦП с весовой избыточностью. Книга рассчитана на научных работников, аспирантов и инженеров, занимающихся разработкой высокоточных быстродействующих аналого-цифровых преобразователей.The book deals with the issue of building high-performance ADC with weight redundancy and variable successive approximation cycle duration. The paper investigates the proposed methods of increasing productivity successive ADC with weight redundancy. The book is intended for scientists, graduate students and engineers involved in the development of high-speed analog-to-digital converters

Minimal Power Latch for Single-Slope ADCs

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example

Methods and Devices for Modifying Active Paths in a K-Delta-1-Sigma Modulator

The invention relates to an improved K-Delta-1-Sigma Modulators (KG1Ss) that achieve multi GHz sampling rates with 90 nm and 45 nm CMOS processes, and that provide the capability to balance performance with power in many applications. The improved KD1Ss activate all paths when high performance is needed (e.g. high bandwidth), and reduce the effective bandwidth by shutting down multiple paths when low performance is required. The improved KD1Ss can adjust the baseband filtering for lower bandwidth, and can provide large savings in power consumption while maintaining the communication link, which is a great advantage in space communications. The improved KD1Ss herein provides a receiver that adjusts to accommodate a higher rate when a packet is received at a low bandwidth, and at a initial lower rate, power is saved by turning off paths in the KD1S Analog to Digital Converter, and where when a higher rate is required, multiple paths are enabled in the KD1S to accommodate the higher band widths

Method and Apparatus for Improving the Resolution of Digitally Sampled Analog Data

A system and method is described for converting an analog signal into a digital signal. The gain and offset of an ADC is dynamically adjusted so that the N-bits of input data are assigned to a narrower channel instead of the entire input range of the ADC. This provides greater resolution in the range of interest without generating longer digital data strings

High Order Modulation Protograph Codes

Digital communication coding methods for designing protograph-based bit-interleaved code modulation that is general and applies to any modulation. The general coding framework can support not only multiple rates but also adaptive modulation. The method is a two stage lifting approach. In the first stage, an original protograph is lifted to a slightly larger intermediate protograph. The intermediate protograph is then lifted via a circulant matrix to the expected codeword length to form a protograph-based low-density parity-check code

Asymmetric soft-error resistant memory

A memory system is provided, of the type that includes an error-correcting circuit that detects and corrects, that more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from '1' to '0' is far more likely than a switch from '0' to'1'. An asymmetric error correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error correcting code

Serial turbo trellis coded modulation using a serially concatenated coder

A coding system uses a serially concatenated coder driving an interleaver, which drives a trellis coder. This combination, while similar to a turbo coder, produces certain different characteristics